Debanjali Nath

According to our database, Debanjali Nath authored at least 8 papers between 2013 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

FPGA and ASIC realisation of EMD algorithm for real-time signal processing.

Kaushik Das, Debanjali Nath, Sambhu Nath Pradhan

IET Circuits Devices Syst., 2020

2017

Leakage Reduction of SRAM-Based Look-Up Table Using Dynamic Power Gating.

Abhishek Nag, Debanjali Nath, Sambhu Nath Pradhan

J. Circuits Syst. Comput., 2017

Transistor level realisation of power gated FSM.

Sambhu Nath Pradhan, Priyanka Choudhury, Debanjali Nath

Int. J. Comput. Aided Eng. Technol., 2017

2016

Hybrid Approach of Within-Clock Power Gating and Normal Power Gating to Reduce Power.

Debanjali Nath, Priyanka Choudhury, Sambhu Nath Pradhan

J. Circuits Syst. Comput., 2016

2015

Layout-oriented look up table-based dual threshold approach to reduce leakage.

Sambhu Nath Pradhan, Angshuman Chakraborty, Abhishek Nag, Debanjali Nath

Int. J. Comput. Aided Eng. Technol., 2015

Thermal aware AND-OR-XOR network synthesis.

Priyanka Choudhury, Debanjali Nath, Vivek Rai, Sambhu Nath Pradhan

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2014

Power gating architecture implementation inside clock period to reduce power.

Debanjali Nath, Priyanka Choudhury, Abhishek Nag, Sambhu Nath Pradhan

Int. J. Comput. Aided Eng. Technol., 2014

2013

Power Reduction by Integrated Within_Clock_Power Gating and Power Gating (WCPG_in_PG).

Debanjali Nath, Priyanka Choudhury, Sambhu Nath Pradhan

Proceedings of the VLSI Design and Test, 17th International Symposium, 2013