Debaleena Das

According to our database1, Debaleena Das authored at least 7 papers between 1997 and 2000.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2000
Reducing test data volume using external/LBIST hybrid test patterns.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes.
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

1999
Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes.
J. Electron. Test., 1999

Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

A Low Cost Approach for Detecting, Locating, and Avoiding Interconnect Faults in FPGA-Based Reconfigurable Systems.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Fault diagnosis in scan-based BIST using both time and space information.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1997
Exhaustive and Near-Exhaustive Memory Testing Techniques and their BIST Implementations.
J. Electron. Test., 1997


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