Dean L. Lewis

According to our database, Dean L. Lewis authored at least 12 papers between 2007 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory).

Daehyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim

IEEE Trans. Computers, 2015

2012

Design for pre-bond testability in 3D integrated circuits.

Dean L. Lewis

PhD thesis, 2012

3D-MAPS: 3D Massively parallel processor with stacked memory.

Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs.

Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung Kyu Lim

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores.

Dean L. Lewis, Shreepad Panth, Xin Zhao, Sung Kyu Lim, Hsien-Hsin S. Lee

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2010

An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth.

Dong Hyuk Woo, Nak Hee Seong, Dean L. Lewis, Hsien-Hsin S. Lee

Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory.

Michael B. Healy, Krit Athikulwongse, Rohan Goel, Mohammad M. Hossain, Dae Hyun Kim, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Moongon Jung, Brian Ouellette, Mohit Pathak, Hemant Sane, Guanhao Shen, Dong Hyuk Woo, Xin Zhao, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

High Performance Non-blocking Switch Design in 3D Die-Stacking Technology.

Dean L. Lewis, Sudhakar Yalamanchili, Hsien-Hsin S. Lee

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Testing Circuit-Partitioned 3D IC Designs.

Dean L. Lewis, Hsien-Hsin S. Lee

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Pre-bond testable low-power clock tree design for 3D stacked ICs.

Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung Kyu Lim

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Architectural evaluation of 3D stacked RRAM caches.

Dean L. Lewis, Hsien-Hsin S. Lee

Proceedings of the IEEE International Conference on 3D System Integration, 2009

2007

A scanisland based design enabling prebond testability in die-stacked microprocessors.

Dean L. Lewis, Hsien-Hsin S. Lee

Proceedings of the 2007 IEEE International Test Conference, 2007