De-Shiuan Chiou

According to our database1, De-Shiuan Chiou authored at least 4 papers between 2006 and 2010.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2010
Sleep Transistor Sizing for Leakage Power Minimization Considering Temporal Correlation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2009
Sleep Transistor Sizing for Leakage Power Minimization Considering Charge Balancing.
IEEE Trans. Very Large Scale Integr. Syst., 2009

2007
Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization.
Proceedings of the 44th Design Automation Conference, 2007

2006
Timing driven power gating.
Proceedings of the 43rd Design Automation Conference, 2006


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