Dayane Reis
Orcid: 0000-0002-8571-1308
According to our database1,
Dayane Reis
authored at least 30 papers
between 2015 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
Accelerating Finite-Field and Torus Fully Homomorphic Encryption via Compute-Enabled (S)RAM.
IEEE Trans. Computers, October, 2024
A Computing-in-Memory-Based One-Class Hyperdimensional Computing Model for Outlier Detection.
IEEE Trans. Computers, June, 2024
Shared-PIM: Enabling Concurrent Computation and Data Flow for Faster Processing-in-DRAM.
CoRR, 2024
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
2023
An Energy-Efficient Computing-in-Memory (CiM) Scheme Using Field-Free Spin-Orbit Torque (SOT) Magnetic RAMs.
IEEE Trans. Emerg. Top. Comput., 2023
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Des. Test, 2022
Hardware-aware Automated Architecture Search for Brain-inspired Hyperdimensional Computing.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
2021
Exploiting FeFETs via Cross-Layer Design from In-memory Computing Circuits to Meta-Learning Applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Attention-in-Memory for Few-Shot Learning with Configurable Ferroelectric FET Arrays.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
Eva-CiM: A System-Level Performance and Energy Evaluation Framework for Computing-in-Memory Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Algorithmic Acceleration of B/FV-like Somewhat Homomorphic Encryption for Compute-Enabled RAM.
IACR Cryptol. ePrint Arch., 2020
IEEE Des. Test, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
A Fast and Energy Efficient Computing-in-Memory Architecture for Few-Shot Learning Applications.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
Eva-CiM: A System-Level Energy Evaluation Framework for Computing-in-Memory Architectures.
CoRR, 2019
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Accelerating Deep Neural Networks in Processing-in-Memory Platforms: Analog or Digital Approach?
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
The Impact of Emerging Technologies on Architectures and System-level Management: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
2018
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015