Dawen Xu

Affiliations:
  • Hefei University of Technology, Anhui, China
  • Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, China


According to our database1, Dawen Xu authored at least 29 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
HyQA: Hybrid Near-Data Processing Platform for Embedding Based Question Answering System.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
Accelerating Deformable Convolution Networks with Dynamic and Irregular Memory Accesses.
ACM Trans. Design Autom. Electr. Syst., July, 2023

2022
Taming Process Variations in CNFET for Efficient Last-Level Cache Design.
IEEE Trans. Very Large Scale Integr. Syst., 2022

HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Canopy: A CNFET-based Process Variation Aware Systolic DNN Accelerator.
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

MOCCA: A Process Variation Tolerant Systolic DNN Accelerator using CNFETs in Monolithic 3D.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021
Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System.
IEEE Trans. Very Large Scale Integr. Syst., 2021

R2F: A Remote Retraining Framework for AIoT Processors With Computing Errors.
IEEE Trans. Very Large Scale Integr. Syst., 2021

EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks.
IEEE Trans. Computers, 2021

Approximate multipliers based on a novel unbiased approximate 4-2 compressor.
Integr., 2021

Taming Process Variations in CNFET for Efficient Last Level Cache Design.
CoRR, 2021

Energy-Efficient Accelerator Design for Deformable Convolution Networks.
CoRR, 2021

RECOIN: A Low-Power Processing-in-ReRAM Architecture for Deformable Convolution.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020
Accelerating Generative Neural Networks on Unmodified Deep Learning Processors - A Software Approach.
IEEE Trans. Computers, 2020

A Hybrid Computing Architecture for Fault-tolerant Deep Learning Accelerators.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Multi-task Scheduling for PIM-based Heterogeneous Computing System.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

CNT-Cache: an Energy-Efficient Carbon Nanotube Cache with Adaptive Encoding.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

RaQu: An automatic high-utilization CNN quantization and mapping framework for general-purpose RRAM Accelerator.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Persistent Fault Analysis of Neural Networks on FPGA-based Acceleration System.
Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020

2019
Squeezing the Last MHz for CNN Acceleration on FPGAs.
Proceedings of the IEEE International Test Conference in Asia, 2019

Exploring emerging CNFET for efficient last level cache design.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Resilient Neural Network Training for Accelerators with Computing Errors.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018
MTTF-Aware Reliability Task Scheduling for PIM-Based Heterogeneous Computing System.
Proceedings of the IEEE International Test Conference in Asia, 2018

FCN-engine: accelerating deconvolutional layers in classic CNN processors.
Proceedings of the International Conference on Computer-Aided Design, 2018

2017
Selective off-loading to Memory: Task Partitioning and Mapping for PIM-enabled Heterogeneous Systems.
Proceedings of the Computing Frontiers Conference, 2017

2015
NBTI-induced circuit aging optimization by protectability-aware gate replacement technique.
Proceedings of the 16th Latin-American Test Symposium, 2015

MTTF-Aware Reliability Task Scheduling for Heterogeneous Multicore System.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2015

2014
Test-Quality Optimization for Variable $n$ -Detections of Transition Faults.
IEEE Trans. Very Large Scale Integr. Syst., 2014

2010
nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications.
Proceedings of the 2011 IEEE International Test Conference, 2010


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