Davood Shahrjerdi

Orcid: 0000-0002-5955-1830

Affiliations:
  • New York University, Department of Electrical and Computer Engineering, New York, NY, USA
  • IBM T. J. Watson Research Center, Yorktown Heights, NY, USA
  • University of Texas at Austin, TX, USA (PhD 2008)
  • University of Tehran, Iran


According to our database1, Davood Shahrjerdi authored at least 15 papers between 2005 and 2020.

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Bibliography

2020
An Electrochemical Biochip for Measuring Low Concentrations of Analytes With Adjustable Temporal Resolutions.
IEEE Trans. Biomed. Circuits Syst., 2020

2019
A CMOS Electrochemical Biochip With 32 × 32 Three-Electrode Voltammetry Pixels.
IEEE J. Solid State Circuits, 2019

A CMOS Biosensor Array with 1024 3-Electrode Voltammetry Pixels and 93dB Dynamic Range.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A Wideband Sliding Correlator-Based Channel Sounder with Synchronization in 65 nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Effects of single vacancy defects on 1/f noise in grapbene/b-BN FETs.
Proceedings of the 76th Device Research Conference, 2018

Variability in synthetic MoS<sub>2</sub> devices: Effect of the growth substrate.
Proceedings of the 76th Device Research Conference, 2018

2017
Hybrid CMOS-Graphene Sensor Array for Subsecond Dopamine Detection.
IEEE Trans. Biomed. Circuits Syst., 2017

15.7 Heterogeneous integrated CMOS-graphene sensor array for dopamine detection.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A 700 μW 1GS/s 4-bit folding-flash ADC in 65nm CMOS for wideband wireless communications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
A 700uW 1GS/s 4-bit Folding-Flash ADC in 65nm CMOS for Wideband Wireless Communications.
CoRR, 2016

Security engineering of nanostructures and nanomaterials.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2014
Shielding and securing integrated circuits with sensors.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2012

2010
Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2005
Optimization of the V<sub>T</sub> control method for low-power ultra-thin double-gate SOI logic circuits.
Integr., 2005


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