Davide Tonietto
Orcid: 0000-0002-7319-143X
According to our database1,
Davide Tonietto
authored at least 10 papers
between 1999 and 2024.
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Bibliography
2024
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2024
2022
A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver.
IEEE J. Solid State Circuits, 2022
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the 47th ESSCIRC 2021, 2021
2019
A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 60Gb/s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ/b at 32dB Loss.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2001
IEEE J. Solid State Circuits, 2001
1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999