Davide Sacchetto

According to our database1, Davide Sacchetto authored at least 15 papers between 2010 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2022
Hybrid InP-SiN microring-resonator based tunable laser with high output power and narrow linewidth for high capacity coherent systems.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022

2019
Memory Effects in Multi-terminal Solid State Devices and Their Applications.
Proceedings of the Handbook of Memristor Networks., 2019

2016
Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

2015
Low-voltage read/write circuit design for transistorless ReRAM crossbar arrays in 180nm CMOS technology.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A ultra-low-power FPGA based on monolithically integrated RRAMs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

2013
A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs.
Proceedings of the Design, Automation and Test in Europe, 2013

Towards structured ASICs using polarity-tunable Si nanowire transistors.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review.
Proc. IEEE, 2012

GMS: Generic memristive structure for non-volatile FPGAs.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

2011
Alternative design methodologies for the next generation logic switch.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010
Design aspects of carry lookahead adders with vertically-stacked nanowire transistors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Memristive devices fabricated with silicon nanowire schottky barrier transistors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010


  Loading...