Davide Marano
Orcid: 0000-0001-9433-4199
According to our database1,
Davide Marano
authored at least 26 papers
between 2007 and 2022.
Collaborative distances:
Collaborative distances:
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Bibliography
2022
Single miller capacitor frequency compensation techniques: Theoretical comparison and critical review.
Int. J. Circuit Theory Appl., 2022
2018
High-Performance Three-Stage Single-Miller CMOS OTA With No Upper Limit of C<sub>L</sub>.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Proceedings of the 2018 International Conference on IC Design & Technology, 2018
2017
Novel straightforward and effective extraction methodology for SiPM model parameters.
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
2016
Optimized Active Single-Miller Capacitor Compensation With Inner Half-Feedforward Stage for Very High-Load Three-Stage OTAs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Int. J. Circuit Theory Appl., 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Enhanced analytical model and output dynamic response of SiPM-Based electronic read-outs.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
2015
Design Methodology of Subthreshold Three-Stage CMOS OTAs Suitable for Ultra-Low-Power Low-Area and High Driving Capability.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
A new enhanced PSPICE implementation of the equivalent circuit model of SiPM detectors.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
195-nW 120-dB subthreshold CMOS OTA driving up to 200 pF and occupying only 4.4-10-3 mm2.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A new accurate analytical expression for the SiPM transient response to single photons.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
2011
Self-biased dual-path push-pull output buffer amplifier topology for LCD driver applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
Improved Low-Power High-Speed Buffer amplifier with slew-Rate Enhancement for LCD Applications.
J. Circuits Syst. Comput., 2010
Int. J. Circuit Theory Appl., 2010
Step-response optimisation techniques for low-power, high-load, three-stage operational amplifiers driving large capacitive loads.
IET Circuits Devices Syst., 2010
Low-power dual-active class-AB buffer amplifier with self-biasing network for LCD column drivers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A novel low-power high-speed rail-to-rail class-B buffer amplifier for LCD output drivers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Analytical figure of merit evaluation of RNMC networks for low-power three-stage OTAs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Improved Power-Efficient RNMC Technique with voltage Buffer and Nulling resistors for Low-Power High-Load Three-Stage amplifiers.
J. Circuits Syst. Comput., 2009
A New Advanced RNMC Technique with Dual-active Current and Voltage Buffers for Low-power High-load Three-stage Amplifiers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Step-response Optimization Techniques for Low-power Three-stage Operational Amplifiers for Large Capacitive Load Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
An efficient RNM compensation topology with voltage buffer and nulling resistors for large-capacitive-load three-stage OTAs.
Proceedings of the 16th IEEE International Conference on Electronics, 2009
2007
Improved Reversed Nested Miller Frequency Compensation Technique With Voltage Buffer and Resistor.
IEEE Trans. Circuits Syst. II Express Briefs, 2007