Davide Giri

Orcid: 0000-0003-4101-4516

According to our database1, Davide Giri authored at least 30 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A 400-ns-Settling- Time Hybrid Dynamic Voltage Frequency Scaling Architecture and Its Application in a 22-Core Network-on-Chip SoC in 12-nm FinFET Technology.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024


BlitzCoin: Fully Decentralized Hardware Power Management for Accelerator-Rich SoCs.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

Mozart: Taming Taxes and Composing Accelerators with Shared-Memory.
Proceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques, 2024

2023
SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs.
IEEE Des. Test, December, 2023

A 12nm 18.1TFLOPs/W Sparse Transformer Processor with Entropy-Based Early Exit, Mixed-Precision Predication and Fine-Grained Power Management.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

An Analysis of Accelerator Data-Transfer Modes in NoC-Based SoC Architectures.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2023

PR-ESP: An Open-Source Platform for Design and Programming of Partially Reconfigurable SoCs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

DECADES: A 67mm<sup>2</sup>, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022
Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP.
CoRR, 2022

Accelerators & Security: The Socket Approach.
IEEE Comput. Archit. Lett., 2022

A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

Work-in-Progress: An Open-Source Platform for Design and Programming of Partially Reconfigurable Heterogeneous SoCs.
Proceedings of the International Conference on Compilers, 2022

2021
Accelerator Integration for Open-Source SoC Design.
IEEE Micro, 2021

Applications and Techniques for Fast Machine Learning in Science.
CoRR, 2021

Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

MasterMind: Many-Accelerator SoC Architecture for Real-Time Brain-Computer Interfaces.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

2020
Agile SoC Development with Open ESP.
CoRR, 2020

The MosaicSim Simulator (Full Technical Report).
CoRR, 2020

MosaicSim: A Lightweight, Modular Simulator for Heterogeneous Systems.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

Agile SoC Development with Open ESP : Invited Paper.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

ESP4ML: Platform-Based Design of Systems-on-Chip for Embedded Machine Learning.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

HL5: A 32-bit RISC-V Processor Designed with High-Level Synthesis.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
Teaching Heterogeneous Computing with System-Level Design Methods.
Proceedings of the Workshop on Computer Architecture Education, 2019

Runtime reconfigurable memory hierarchy in embedded scalable platforms.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Parallel and Serial Computation in Nanomagnet Logic: An Overview.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Accelerators and Coherence: An SoC Perspective.
IEEE Micro, 2018

NoC-Based Support of Heterogeneous Cache-Coherence Models for Accelerators.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

2014
A standard cell approach for MagnetoElastic NML circuits.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014


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