David Novo

Konstantinos Kanellopoulos

Proceedings of the Computer, Communication, and Signal Processing. AI, Knowledge Engineering and IoT for Smart Systems, 2023

2022

Approximations in Deep Learning.

[BibT_eX]

[DOI]

CoRR, 2022

MemCork: Exploration of Hybrid Memory Architectures for Intermittent Computing at the Edge.

[BibT_eX]

[DOI]

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction.

[BibT_eX]

[DOI]

Rahul Bera

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Flash-Cosmos: In-Flash Bulk Bitwise Operations Using Inherent Computation Capability of NAND Flash Memory.

[BibT_eX]

[DOI]

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Sibyl: adaptive and extensible data placement in hybrid storage systems using online reinforcement learning.

[BibT_eX]

[DOI]

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

Demystifying the TensorFlow Eager Execution of Deep Learning Inference on a CPU-GPU Tandem.

[BibT_eX]

[DOI]

Paul Delestrac

Lionel Torres

Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

Pref-X: a framework to reveal data prefetching in commercial in-order cores.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

A Heuristic Exploration of Retraining-free Weight-Sharing for CNN Compression.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Fast Exploration of Weight Sharing Opportunities for CNN Compression.

[BibT_eX]

[DOI]

CoRR, 2021

An FPGA-based Emulation Platform for Edge Computing Node Design Exploration.

[BibT_eX]

[DOI]

Theo Soriano

Pascal Benoit

Proceedings of the IEEE International Workshop on Rapid System Prototyping, 2021

Implementing Rowhammer Memory Corruption in the gem5 Simulator.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Workshop on Rapid System Prototyping, 2021

Virtual Platform to Analyze the Security of a System on Chip at Microarchitectural Level.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Symposium on Security and Privacy Workshops, 2021

Transit-Guard: An OS-based Defense Mechanism Against Transient Execution Attacks.

[BibT_eX]

[DOI]

Muhammad Khurram Bhatti

Proceedings of the 26th IEEE European Test Symposium, 2021

Diminisher: A Linux Kernel Based Countermeasure for TAA Vulnerability.

[BibT_eX]

[DOI]

Proceedings of the Computer Security. ESORICS 2021 International Workshops, 2021

AdequateDL: Approximating Deep Learning Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

Memory Hierarchy Calibration Based on Real Hardware In-order Cores for Accurate Simulation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Vulnerability Assessment of the Rowhammer Attack Using Machine Learning and the gem5 Simulator - Work in Progress.

[BibT_eX]

[DOI]

Proceedings of the SAT-CPS@CODASPY 2021, 2021

2020

Sensitivity Analysis and Compression Opportunities in DNNs Using Weight Sharing.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020

On the Automatic Exploration of Weight Sharing for Deep Neural Network Compression.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Exploration of Performance and Energy Trade-offs for Heterogeneous Multicore Architectures.

[BibT_eX]

[DOI]

CoRR, 2019

2018

Evaluation of Heterogeneous Multicore Cluster Architectures Designed for Mobile Computing.

[BibT_eX]

[DOI]

Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018

Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Improving the Performance of STT-MRAM LLC Through Enhanced Cache Replacement Policy.

[BibT_eX]

[DOI]

Proceedings of the Architecture of Computing Systems - ARCS 2018, 2018

Progressive Generation of Canonical Irredundant Sums of Products Using a SAT Solver.

[BibT_eX]

[DOI]

Proceedings of the Advanced Logic Synthesis, 2018

2017

Design Space Exploration of LDPC Decoders Using High-Level Synthesis.

[BibT_eX]

[DOI]

IEEE Access, 2017

2016

A Workflow for Fast Evaluation of Mapping Heuristics Targeting Cloud Infrastructures.

[BibT_eX]

[DOI]

CoRR, 2016

Speed and accuracy dilemma in NoC simulation: What about memory impact?

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2015

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs.

[BibT_eX]

[DOI]

Muhsen Owaida

Gabriel Falcão

João Andrade

Christos D. Antonopoulos

Nikolaos Bellas

Madhura Purnaprajna

Georgios Karakonstantis

Andreas Burg

ACM Trans. Embed. Comput. Syst., 2015

Libra: Software-Controlled Cell Bit-Density to Balance Wear in NAND Flash.

[BibT_eX]

[DOI]

François-Xavier Standaert

ACM Trans. Embed. Comput. Syst., 2015

Automatic Application of Power Analysis Countermeasures.

[BibT_eX]

[DOI]

Vítor Manuel Mendes da Silva

IEEE Trans. Computers, 2015

FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction.

[BibT_eX]

[DOI]

Proceedings of the Hardware and Software: Verification and Testing, 2015

Improved carry chain mapping for the VTR flow.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

A technology mapper for depth-constrained FPGA logic cells.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Automatic support for multi-module parallelism from computational patterns.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis.

[BibT_eX]

[DOI]

Gabriel Falcão Paiva Fernandes

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC Decoders.

[BibT_eX]

[DOI]

Vítor Manuel Mendes da Silva

Gabriel Falcão Paiva Fernandes

Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Retraining-based timing error mitigation for hardware neural networks.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Constrained interpolation for guided logic synthesis.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Hardware system synthesis from Domain-Specific Languages.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Revisiting and-inverter cones.

[BibT_eX]

[DOI]

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Wear unleveling: improving NAND flash lifetime by balancing page endurance.

[BibT_eX]

[DOI]

Proceedings of the 12th USENIX conference on File and Storage Technologies, 2014

Energy efficient MIMO processing: A case study of opportunistic run-time approximations.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

SKETCHILOG: Sketching combinational circuits.

[BibT_eX]

[DOI]

Andrew Becker

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Cracking the complexity of fixed-point refinement in complex wireless systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Making domain-specific hardware synthesis tools cost-efficient.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Shadow And-Inverter Cones.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only).

[BibT_eX]

[DOI]

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Accuracy vs speed tradeoffs in the estimation of fixed-point errors on linear time-invariant systems.

[BibT_eX]

[DOI]

Sara El Alaoui

Proceedings of the Design, Automation and Test in Europe, 2013

Phœnix: reviving MLC blocks as SLC to extend NAND flash devices lifetime.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

An EDA-friendly protection scheme against side-channel attacks.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Sleuth: Automated Verification of Software Power Analysis Countermeasures.

[BibT_eX]

[DOI]

Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2013, 2013

Automated circuit elaboration from incomplete architectural descriptions.

[BibT_eX]

[DOI]

Andrew Becker

Proceedings of the 2013 Asilomar Conference on Signals, 2013

2012

Quantization of VLSI digital signal processing systems.

[BibT_eX]

[DOI]

EURASIP J. Adv. Signal Process., 2012

Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter cones.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case.

[BibT_eX]

[DOI]

Christos D. Antonopoulos

Georgios Karakonstantis

Andreas Burg

Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

Selective flexibility: Breaking the rigidity of datapath merging.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Software controlled cell bit-density to improve NAND flash lifetime.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

Energy Aware Signal Processing for Software Defined Radio Baseband Implementation.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2011

Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2011

2010

Ultra low energy Domain Specific Instruction-set Processor for on-line surveillance.

[BibT_eX]

[DOI]

Angeliki Kritikakou

Praveen Raghavan

Jos Huisken

Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

Fast performance evaluation of fixed-point systems with un-smooth operators.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Quantization mode opportunities in fixed-point system design.

[BibT_eX]

[DOI]

Proceedings of the 18th European Signal Processing Conference, 2010

Adaptive early-stopping threshold for LTE turbo decoder.

[BibT_eX]

[DOI]

Proceedings of the 18th European Signal Processing Conference, 2010

Exploiting finite precision information to guide data-flow mapping.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

2009

Energy-performance Exploration of a CGA-based SDR Processor.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2009

Generic Multiphase Software Pipelined Partial FFT on Instruction Level Parallel Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2009

Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

Novel energy-efficient scalable soft-output SSFE MIMO detector architectures.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

A System Level Algorithmic Approach toward Energy-Aware SDR Baseband Implementations.

[BibT_eX]

[DOI]

Proceedings of IEEE International Conference on Communications, 2009

Finite precision processing in wireless applications.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Algorithm-architecture co-design of soft-output ML MIMO detector for parallel application specific instruction set processors.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Application-driven adaptive fixed-point refinement for SDRs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

An implementation friendly low complexity multiplierless LLR generator for soft MIMO sphere decoders.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

Selective Spanning with Fast Enumeration: A Near Maximum-Likelihood MIMO Detector Designed for Parallel Programmable Baseband Architectures.

[BibT_eX]

[DOI]

Eduardo Lopez-Estraviz

André Bourdoux

Proceedings of IEEE International Conference on Communications, 2008

Bridging the energy gap in size, weight and power constrained software defined radio: Agile baseband processing as a key enabler.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2008

Adaptive SSFE Near-ML MIMO Detector with Dynamic Search Range and 80-103Mbps Flexible Implementation.

[BibT_eX]

[DOI]

Proceedings of the Global Communications Conference, 2008. GLOBECOM 2008, New Orleans, LA, USA, 30 November, 2008

Scenario-Based Fixed-point Data Format Refinement to Enable Energy-scalable Software Defined Radios.

[BibT_eX]

[DOI]

Andy Lambrechts

Proceedings of the Design, Automation and Test in Europe, 2008

Generic Multi-Phase Software-Pipelined Partial-FFT on Instruction-Level-Parallel Architectures and SDR Baseband Applications.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Optimizing Near-ML MIMO Detector for SDR Baseband on Parallel Programmable Architectures.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

A Coarse-Grained Array based Baseband Processor for 100Mbps+ Software Defined Radio.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

How to let instruction set processor beat ASIC for low power wireless baseband implementation: a system level approach.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

2007

A Wavelet-FFT Based Efficient Sparse OFDMA Demodulator and Its Implementation on VLIW Architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2007

2006

Software Simultaneous Multi-Threading, a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level Parallelism.

[BibT_eX]

[DOI]

Daniele Paolo Scarpazza

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

A Scalable Baseband Platform for Energy-Efficient Reactive Software-Defined-Radio.

[BibT_eX]

[DOI]