David M. Wu

According to our database, David M. Wu authored at least 14 papers between 1984 and 2006.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2006

A Low Cost, High Quality Embedded Array DFT Technique for High Performance Processors.

Zhuoyu Bao, Suriya A. Kumar, David M. Wu, Vimal K. Natarajan, Mike Lin

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

2004

An Optimized DFT and Test Pattern Generation Strategy for an Intel High Performance Microprocessor.

David M. Wu, Mike Lin, Madhukar Reddy, Talal Jaber, Anil Sabbavarapu, Larry Thatcher

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003

H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing.

David M. Wu, Mike Lin, Subhasish Mitra, Kee Sup Kim, Anil Sabbavarapu, Talal Jaber, Pete Johnson, Dale March, Greg Parrish

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002

Trouble With Scan.

David M. Wu

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2000

Cold Delay Defect Screening.

Chao-Wen Tseng, Edward J. McCluskey, Xiaoping Shao, David M. Wu

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

1999

"DFY and DFR are more important than DFT".

David M. Wu

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

DFT is all I can afford, who cares about Design for Yield or Design for Reliability!

David M. Wu

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1992

Multiple redundancy removal during test generation and synthesis.

David M. Wu, Robert M. Swanson

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

1991

Testing the impact of process defects on ECL power-delay performance.

Jiann-Shiun Yuan, Juin J. Liou, David M. Wu

Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

An optimized delay testing technique for LSSD-based VLSI logic circuits.

David M. Wu

Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

Statistical sensitivity simulation for integrating design and testing of MOSFET integrated circuits.

Waisum Wong, Juin J. Liou, Jiann-Shiun Yuan, David M. Wu

Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

Delay Test Effectiveness Evaluation of LSSD-Based VLSI Vogic Circuits.

David M. Wu, Charles E. Radke

Proceedings of the 28th Design Automation Conference, 1991

1986

Statistical AC Test Coverage.

David M. Wu, Charles E. Radke, J. Paul Roth

Proceedings of the Proceedings International Test Conference 1986, 1986

1984

Improve Yield and Quality Through Testability Analysis of VLSI Circuits.

David M. Wu, Charles E. Radke, C. C. Beh

Proceedings of the Proceedings International Test Conference 1984, 1984