David M. Lewis

According to our database, David M. Lewis authored at least 46 papers between 1985 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2019

Spatial Timing Analysis With Exact Propagation of Delay and Application to FPGA Performance.

David M. Lewis, Herman Schmit

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2017

3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration.

David Greenhill, Ron Ho, David M. Lewis, Herman Schmit, Kok Hong Chan, Andy Tong, Sean Atsatt, Dana How, Peter McElheny, Keith Duwel, Jeffrey Schulz, Darren Faulkner, Gopal Iyer, George Chen, Hee Kong Phoon, Han Wooi Lim, Wei-Yee Koay, Ty Garibay

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

The Stratix™ 10 Highly Pipelined FPGA Architecture.

David M. Lewis, Gordon R. Chiu, Jeffrey Chromczak, David R. Galloway, Ben Gamsa, Valavan Manohararajah, Ian Milton, Tim Vanderhoek, John Van Dyken

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Stratix™ 10 High Performance Routable Clock Networks.

Carl Ebeling, Dana How, David M. Lewis, Herman Schmit

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2015

Arria™ 10 device architecture.

Jeffrey Tyhach, Mike Hutton, Sean Atsatt, Arifur Rahman, Brad Vest, David M. Lewis, Martin Langhammer, Sergey Y. Shumarayev, Tim Hoang, Allen Chan, Dong-Myung Choi, Dan Oh, Hae-Chang Lee, Jack Chui, Ket Chiew Sia, Edwin Kok, Wei-Yee Koay, Boon-Jin Ang

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2013

Architectural enhancements in Stratix V™.

David M. Lewis, David Cashman, Mark Chan, Jeffrey Chromczak, Gary Lai, Andy Lee, Tim Vanderhoek, Haiming Yu

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

2011

An Empirical Evaluation of Similarity Coefficients for Binary Valued Data.

David M. Lewis, Vandana Pursnani Janeja

Int. J. Data Warehous. Min., 2011

2010

A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs.

Doris Chen, Deshanand P. Singh, Jeffrey Chromczak, David M. Lewis, Ryan Fung, David Neto, Vaughn Betz

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

2009

Architectural enhancements in Stratix-III^TM and Stratix-IV^TM.

David M. Lewis, Elias Ahmed, David Cashman, Tim Vanderhoek, Christopher Lane, Andy Lee, Philip Pan

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

2005

The Stratix II logic and routing architecture.

David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

2004

Improving FPGA Performance and Area Using an Adaptive Logic Module.

Michael D. Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini

Proceedings of the Field Programmable Logic and Application, 2004

MAX II: A low-cost, high-performance LUT-based CPLD.

Paul Leventis, Brad Vest, Mike Hutton, David M. Lewis

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003

The Stratix^TM routing and logic architecture.

David M. Lewis, Vaughn Betz, David Jefferson, Andy Lee, Christopher Lane, Paul Leventis, Sandy Marquardt, Cameron McClintock, Bruce Pedersen, Giles Powell, Srinivas Reddy, Chris Wysocki, Richard Cliff, Jonathan Rose

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Architecture of datapath-oriented coarse-grain logic and routing for FPGAs.

Andy Gean Ye, Jonathan Rose, David M. Lewis

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

Cyclone ™: a low-cost, high-performance FPGA.

Paul Leventis, Mark Chan, Michael Chan, David M. Lewis, Behzad Nouban, Giles Powell, Brad Vest, Myron Wong, Renxin Xia, John Costello

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002

Synthesizing datapath circuits for FPGAs with emphasis on area minimization.

Andy Gean Ye, Jonathan Rose, David M. Lewis

Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Analytical Framework for Switch Block Design.

Guy G. Lemieux, David M. Lewis

Proceedings of the Field-Programmable Logic and Applications, 2002

Circuit design of routing switches.

Guy G. Lemieux, David M. Lewis

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

2001

Using sparse crossbars within LUT.

Guy G. Lemieux, David M. Lewis

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2001

2000

Generating highly-routable sparse crossbars for PLDs.

Guy G. Lemieux, Paul Leventis, David M. Lewis

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

Design of a VLIW Compute Accelerator on the Transmogrifier-2.

L. Louis Zhang, Qiang Wang, David M. Lewis

Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

1999

Procedural Texture Mapping on FPGAs.

Andy Gean Ye, David M. Lewis

Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

1998

The Transmogrifier-2: a 1 million gate rapid-prototyping system.

David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow

IEEE Trans. Very Large Scale Integr. Syst., 1998

1997

Automated field-programmable compute accelerator design using partial evaluation.

Qiang Wang, David M. Lewis

Proceedings of the 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 1997

1996

DP-FPGA: An FPGA Architecture Optimized for Datapaths.

Don Cherepacha, David M. Lewis

VLSI Design, 1996

Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays.

Vi Cuong Chan, David M. Lewis

Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, 1996

1995

114 MFLOPS logarithmic number system arithmetic unit for DSP applications.

David M. Lewis

IEEE J. Solid State Circuits, December, 1995

1994

Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit.

David M. Lewis

IEEE Trans. Computers, 1994

Routing Architectures for Hierarchical Field Programmable Gate Arrays.

Aditya A. Aggarwal, David M. Lewis

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1993

A multiple-strength multiple-delay compiled-code logic simulator.

Ahmet N. Parlakbilek, David M. Lewis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Highly Selective "Analog" Filters Using Delta Sigma Based IIR Filtering.

David A. Johns, David M. Lewis, Don Cherepacha

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

A Field Programmable Accelerator for Compiled-Code Applications.

David M. Lewis, Marcus van Ierssel, Daniel H. Wong

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

An accurate LNS arithmetic unit using interleaved memory function interpolator.

David M. Lewis

Proceedings of the 11th Symposium on Computer Arithmetic, 29 June, 1993

1992

A compiled-code hardware accelerator for circuit simulation.

David M. Lewis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

1991

A hierarchical compiled code event-driven logic simulator.

David M. Lewis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Hector: A Hierarchically Structured Shared-memory Multiprocessor.

Zvonko G. Vranesic, Michael Stumm, David M. Lewis, Ron White

Computer, 1991

1990

Device model approximation using 2^N trees.

David M. Lewis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

An Architecture for Addition and Subtraction of Long Word Length Numbers in the Logarithmic Number System.

David M. Lewis

IEEE Trans. Computers, 1990

Using Deducibility in Secure Network Modelling.

Brian W. Thomson, E. Stewart Lee, Peter I. P. Boulton, Michael Stumm, David M. Lewis

Proceedings of the ESORICS 90, 1990

1989

Hierarchical compiled event-driven logic simulation.

David M. Lewis

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Algorithm design for a 30-bit integrated logarithmic processor.

David M. Lewis, Lawrence K. Yu

Proceedings of the 9th Symposium on Computer Arithmetic, 1989

1988

Transforming bit-serial communication circuits into fast parallel VLSI implementations.

David M. Lewis, Brian W. Thomson, Peter I. P. Boulton, E. Stewart Lee

IEEE J. Solid State Circuits, April, 1988

Hardware accelerators for timing simulation of VLSI digital circuits.

David M. Lewis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

A Programmable Hardware Accelerator for Compiled Electrical Simulation.

David M. Lewis

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1986

Swamp: A Fast Processor for Smalltalk-80.

David M. Lewis, David R. Galloway, Robert J. Francis, Brian W. Thomson

Proceedings of the Conference on Object-Oriented Programming Systems, 1986

1985

A hardware engine for analogue mode simulation of MOS digital circuits.

David M. Lewis

Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985