David M. Koppelman
According to our database1,
David M. Koppelman
authored at least 26 papers
between 1990 and 2020.
Collaborative distances:
Collaborative distances:
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Bibliography
2020
Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020
2019
Proceedings of the ACM International Conference on Supercomputing, 2019
2018
Thoroughly Exploring GPU Buffering Options for Stencil Code by Using an Efficiency Measure and a Performance Model.
IEEE Trans. Multi Scale Comput. Syst., 2018
2016
Design space exploration for device and architectural heterogeneity in chip-multiprocessors.
Microprocess. Microsystems, 2016
A Performance Model and Efficiency-Based Assignment of Buffering Strategies for Automatic GPU Stencil Code Generation.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016
2015
GeauxDock: A novel approach for mixed-resolution ligand docking using a descriptor-based force field.
J. Comput. Chem., 2015
Chemora: A PDE-Solving Framework for Modern High-Performance Computing Architectures.
Comput. Sci. Eng., 2015
2014
Discovering barriers to efficient execution, both obvious and subtle, using instruction-level visualization.
Proceedings of the First Workshop on Visual Performance Analysis, 2014
2013
From physics model to results: An optimizing framework for cross-architecture code generation.
Sci. Program., 2013
2012
J. Circuits Syst. Comput., 2012
2011
Efficient Prefetching with Hybrid Schemes and Use of Program Feedback to Adjust Prefetcher Aggressiveness.
J. Instr. Level Parallelism, 2011
A Massive Data Parallel Computational Framework for Petascale/Exascale Hybrid Computer Systems.
Proceedings of the Applications, Tools and Techniques on the Road to Exascale Computing, Proceedings of the conference ParCo 2011, 31 August, 2011
2010
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010
2009
Proceedings of the 28th International Performance Computing and Communications Conference, 2009
2008
J. Syst. Archit., 2008
2007
Memory Performance and Scalability of Intel's and AMD's Dual-Core Processors: A Case Study.
Proceedings of the 26th IEEE International Performance Computing and Communications Conference, 2007
2000
Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), 2000
1997
J. Parallel Distributed Comput., 1997
1996
IEEE Trans. Parallel Distributed Syst., 1996
Congested Banyan network analysis using congested-queue states and neighboring-queue effects.
IEEE/ACM Trans. Netw., 1996
A Lower Bound on the Average Physical Length of Edges in the Physical Realization of Graphs.
Parallel Process. Lett., 1996
1994
Reducing PE/Memory Traffic in Multiprocessors by the Difference Coding of Memory Addresses.
IEEE Trans. Parallel Distributed Syst., 1994
IEEE Trans. Inf. Theory, 1994
1992
Reducing PE/Memory Traffic in Shared Memory Multiprocessors by the Difference Coding of Addresses.
Proceedings of the 1992 International Conference on Parallel Processing, 1992
1990