David Levacq
According to our database1,
David Levacq
authored at least 8 papers
between 2005 and 2024.
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Collaborative distances:
Timeline
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2024
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2024
112-Gbps High Speed Serial Links to Interconnect Direct RF Sampling ADCs and Digital High Throughput Satellite Processors.
Proceedings of the IEEE International Mediterranean Conference on Communications and Networking, 2024
2008
IEEE J. Solid State Circuits, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder.
J. Multiple Valued Log. Soft Comput., 2007
IEEE J. Solid State Circuits, 2007
Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
A Wide Range Spatial Frequency Analysis of Intra-Die Variations with 4-mm 4000 × 1 Transistor Arrays in 90nm CMOS.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005