David Levacq

According to our database1, David Levacq authored at least 8 papers between 2005 and 2024.

Collaborative distances:

Timeline

2006
2008
2010
2012
2014
2016
2018
2020
2022
2024
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Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
112-Gbps High Speed Serial Links to Interconnect Direct RF Sampling ADCs and Digital High Throughput Satellite Processors.
Proceedings of the IEEE International Mediterranean Conference on Communications and Networking, 2024

2008
Backgate Bias Accelerator for sub-100 ns Sleep-to-Active Modes Transition Time.
IEEE J. Solid State Circuits, 2008

1/5 power reduction by global optimization based on fine-grained body biasing.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder.
J. Multiple Valued Log. Soft Comput., 2007

Low Leakage SOI CMOS Static Memory Cell With Ultra-Low Power Diode.
IEEE J. Solid State Circuits, 2007

Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

A Wide Range Spatial Frequency Analysis of Intra-Die Variations with 4-mm 4000 × 1 Transistor Arrays in 90nm CMOS.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2005
Ultra-low power flip-flops for MTCMOS circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005


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