David Kinniment

According to our database1, David Kinniment authored at least 39 papers between 1968 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2011
Sub-threshold synchronizer.
Microelectron. J., 2011

2010
Extending Synchronization from Super-Threshold to Sub-threshold Region.
Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems, 2010

2009
Synchronization and Arbitration in GALS.
Proceedings of the 4th International Workshop on the Application of Formal Methods for Globally Asynchronous and Locally Synchronous Design, 2009

On the trade-off between resolution time and delay times in bistable circuits.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
On-Chip Measurement of Deep Metastability in Synchronizers.
IEEE J. Solid State Circuits, 2008

High resolution flash time-to-digital converter with sub-picosecond measurement capabilities.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

Adapting Synchronizers to the Effects of on Chip Variability.
Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008

2007
Measuring Deep Metastability and Its Effect on Synchronizer Performance.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Built-in time measurement circuits - a comparative design study.
IET Comput. Digit. Tech., 2007

Embedded high-resolution delay measurement system using time amplification.
IET Comput. Digit. Tech., 2007

NoC Communication Strategies Using Time-to-Digital Conversion.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

A High Resolution Flash Time-to-Digital Converter Taking Into Account Process Variability.
Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007

2006
A Robust Synchronizer.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Measuring Deep Metastability.
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006

2004
Low Latency Synchronization Through Speculation.
Proceedings of the Integrated Circuit and System Design, 2004

Design of Sub-10-Picoseconds On-Chip Time Measurement Circuit.
Proceedings of the 2004 Design, 2004

2003
On-chip structures for timing measurement and test.
Microprocess. Microsystems, 2003

2002
Synchronization circuit performance.
IEEE J. Solid State Circuits, 2002

Analysis of the oscillation problem in tri-flops.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

On-Chip Structures for Timing Measurements and Test.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

2000
Synchronous and asynchronous A-D conversion.
IEEE Trans. Very Large Scale Integr. Syst., 2000

Asynchronous Communication Mechanisms Using Self-Timed Circuits.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

Priority Arbiters.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

1999
A statechart based HW/SW codesign system.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998
Towards Asynchronous A-D Conversion.
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998

1996
An evaluation of asynchronous addition.
IEEE Trans. Very Large Scale Integr. Syst., 1996

Application-specific processor architectures for embedded control: case studies.
Microprocess. Microsystems, 1996

Modelling, analysis and synthesis of asynchronous control circuits using Petri nets.
Integr., 1996

Time Wizard: A Design and Assessment Tool for Real-Time Applications.
Proceedings of the Eighth Euromicro Workshop on Real-Time Systems, 1996

A self-taught computer engineering course.
Proceedings of the ACM SIGCSE 1st Australasian Conference on Computer Science Education, 1996

1992
SIMSTRICT: A Behavioural Simulator for Use with the STRICT Hardware Description Language (Short Note).
Comput. J., 1992

Modelling and Verification of Timing Conditions with the Boyer Moore Prover.
Proceedings of the Theorem Provers in Circuit Design, 1992

1991
Correct interactive transformational synthesis of DSP hardware.
Proceedings of the conference on European design automation, 1991

1984
A recursive design methodology for VLSI: Theory and example.
Integr., 1984

Reduced-instruction set multi-microcomputer system.
Proceedings of the American Federation of Information Processing Societies: 1984 National Computer Conference, 1984

1983
An autolayout system for a hierarchical i.c. design environment.
Integr., 1983

1978
A Design Language for Asynchronous Logic.
Comput. J., 1978

1971
An Experimental Paging Unit.
Comput. J., 1971

1968
Associative memories in large computer systems <i>and</i> An integrated associateve memory matrix.
Proceedings of the Information Processing, Proceedings of IFIP Congress 1968, Edinburgh, UK, 5-10 August 1968, Volume 2, 1968


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