David K. Su

According to our database1, David K. Su authored at least 31 papers between 1998 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2013
A 30.3dBm 1.9GHz-bandwidth 2×4-array stacked 5.3GHz CMOS power amplifier.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A compact 120-MHz 1.8V/1.2V dual-output DC-DC converter with digital control.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2011

A quadrature LO generator using bidirectionally-coupled oscillators for 60-GHz applications.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
A Calibration-Free 800 MHz Fractional-N Digital PLL With Embedded TDC.
IEEE J. Solid State Circuits, 2010

A calibration-free 800MHz fractional-N digital PLL with embedded TDC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A stacked 6.5-GHz 29.6-dBm power amplifier in standard 65-nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
A 5-GHz Wireless LAN Transmitter with Integrated Tunable High-Q RF Filter.
IEEE J. Solid State Circuits, 2009

A 0.7-V 870-µW Digital-Audio CMOS Sigma-Delta Modulator.
IEEE J. Solid State Circuits, 2009

Design and implementation of a CMO 802.11n SoC.
IEEE Commun. Mag., 2009

A 1x1 802.11n WLAN SoC with fully integrated RF front-end utilizing PA linearization.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008
A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN.
IEEE J. Solid State Circuits, 2008

A Digitally Modulated Polar CMOS Power Amplifier With a 20-MHz Channel Bandwidth.
IEEE J. Solid State Circuits, 2008


2007
Challenges in Designing CMOS Wireless Systems-on-a-Chip.
IEICE Trans. Electron., 2007

A Digitally Modulated Polar CMOS PA with 20MHz Signal BW.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A Fully Integrated RF Front-End with Independent RX/TX Matching and +20dBm Output Power for WLAN Applications.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
A 1.9-GHz Single-Chip CMOS PHS Cellphone.
IEEE J. Solid State Circuits, 2006

A CMOS oversampled DAC with multi-bit semi-digital filtering and boosted subcarrier SNR for ADSL central office modems.
IEEE J. Solid State Circuits, 2006

A 1.9GHz Single-Chip CMOS PHS Cellphone.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
A low-voltage low-power sigma-delta modulator for broadband analog-to-digital conversion.
IEEE J. Solid State Circuits, 2005

An 802.11g WLAN SoC.
IEEE J. Solid State Circuits, 2005

A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC.
IEEE J. Solid State Circuits, 2005

2004
A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g wireless LAN.
IEEE J. Solid State Circuits, 2004

A CMOS oversampling bandpass cascaded D/A converter with digital FIR and current-mode semi-digital filtering.
IEEE J. Solid State Circuits, 2004

A 1.2-V 15-bit 2.5-MS/s oversampling ADC with reduced integrator swings.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2002
A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN systems.
IEEE J. Solid State Circuits, 2002

A CMOS RF power amplifier with parallel amplification for efficient power control.
IEEE J. Solid State Circuits, 2002

2001
Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiver.
IEEE J. Solid State Circuits, 2001

1998
An IC for linearizing RF power amplifiers using envelope elimination and restoration.
IEEE J. Solid State Circuits, 1998

Substrate noise coupling through planar spiral inductor.
IEEE J. Solid State Circuits, 1998


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