David Ihsin Cheng

According to our database1, David Ihsin Cheng authored at least 14 papers between 1994 and 2003.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2003
Further improve circuit partitioning using GBAW logic perturbation techniques.
IEEE Trans. Very Large Scale Integr. Syst., 2003

2001
Further improve circuit partitioning using GBAW logic perturbation techniques.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Circuit partitioning with coupled logic restructuring techniques.
Proceedings of ASP-DAC 2000, 2000

1999
Efficient Boolean division and substitution using redundancy addition and removing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

1998
A hybrid methodology for switching activities estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

On Removing Multiple Redundancies in Combinational Circuits.
Proceedings of the 1998 Design, 1998

Efficient Boolean Division and Substitution.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1996
A New Hybrid Methodology for Power Estimation.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Circuit partitioning with logic perturbation.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Logic rectification and synthesis for engineering change.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994
On the Verification of Function Equivalence with unknown Input Correspondence.
J. Circuits Syst. Comput., 1994

Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Error Diagnosis for Transistor-Level Verification.
Proceedings of the 31st Conference on Design Automation, 1994


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