David H. Albonesi

Christina Delimitrou

Gonzalo Gonzalez-Pumariega

CoRR, 2020

MatRaptor: A Sparse-Sparse Matrix Multiplication Accelerator Based on Row-Wise Product.

[BibT_eX]

[DOI]

Nitish Kumar Srivastava

Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

CuttleSys: Data-Driven Resource Management for Interactive Services on Reconfigurable Multicores.

[BibT_eX]

[DOI]

Neeraj Kulkarni

Amulya Khurana

Christina Delimitrou

Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

Tensaurus: A Versatile Accelerator for Mixed Sparse-Dense Tensor Computations.

[BibT_eX]

[DOI]

Nitish Kumar Srivastava

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

2019

T2S-Tensor: Productively Generating High-Performance Spatial Hardware for Dense Tensor Computations.

[BibT_eX]

[DOI]

Nitish Kumar Srivastava

Christopher J. Hughes

Timothy G. Mattson

Pradeep Dubey

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2017

Toolbox for exploration of energy-efficient event processors for human-computer interaction.

[BibT_eX]

[DOI]

Tayyar Rzayev

François Guimbretière

Rajit Manohar

Jaeyeon Kihm

Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

DeepRecon: Dynamically reconfigurable architecture for accelerating deep neural networks.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Dynamic GPGPU Power Management Using Adaptive Model Predictive Control.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

2016

2015 International Symposium on Computer Architecture Influential Paper Award.

[BibT_eX]

[DOI]

IEEE Micro, 2016

Characterizing the Benefits and Limitations of Smart Building Meeting Room Scheduling.

[BibT_eX]

[DOI]

Abhinandan Majumdar

Zhiru Zhang

Proceedings of the 7th ACM/IEEE International Conference on Cyber-Physical Systems, 2016

2014

Energy-comfort optimization using discomfort history and probabilistic occupancy prediction.

[BibT_eX]

[DOI]

Proceedings of the International Green Computing Conference, 2014

2013

Flicker: a dynamically adaptive architecture for power limited multicore systems.

[BibT_eX]

[DOI]

Paula Petrica

Adam M. Izraelevitz

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

2012

Energy-aware meeting scheduling algorithms for smart buildings.

[BibT_eX]

[DOI]

Abhinandan Majumdar

Pradip Bose

Proceedings of the BuildSys '12 Proceedings of the Fourth ACM Workshop on Embedded Sensing Systems for Energy-Efficiency in Buildings, 2012

2011

ReMAP: A Reconfigurable Architecture for Chip Multiprocessors.

[BibT_eX]

[DOI]

IEEE Micro, 2011

A phase adaptive cache hierarchy for SMT processors.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2011

A low-latency, high-throughput on-chip optical router architecture for future chip multiprocessors.

[BibT_eX]

[DOI]

Mark J. Cianchetti

ACM J. Emerg. Technol. Comput. Syst., 2011

2010

Moving Forward.

[BibT_eX]

[DOI]

IEEE Micro, 2010

Future Directions in Computer Architecture Research.

[BibT_eX]

[DOI]

IEEE Micro, 2010

ReMAP: A Reconfigurable Heterogeneous Multicore Architecture.

[BibT_eX]

[DOI]

Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Adaptive Cache Memories for SMT Processors.

[BibT_eX]

[DOI]

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Scalable thread scheduling and global power management for heterogeneous many-core architectures.

[BibT_eX]

[DOI]

Jonathan A. Winter

Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

Dynamically managed multithreaded reconfigurable architectures for chip multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009

From the Editor in Chief: Welcome A-Board.

[BibT_eX]

[DOI]

IEEE Micro, 2009

Phastlane: a rapid transit optical routing network.

[BibT_eX]

[DOI]

Mark J. Cianchetti

Joseph C. Kerekes

Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

2008

Addressing thermal nonuniformity in SMT workloads.

[BibT_eX]

[DOI]

Jonathan A. Winter

ACM Trans. Archit. Code Optim., 2008

Changes Ahead.

[BibT_eX]

[DOI]

IEEE Micro, 2008

Shared reconfigurable architectures for CMPS.

[BibT_eX]

[DOI]

Mark J. Cianchetti

Proceedings of the FPL 2008, 2008

Scheduling algorithms for unpredictably heterogeneous CMP architectures.

[BibT_eX]

[DOI]

Jonathan A. Winter

Proceedings of the 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2008

2007

On-Chip Optical Technology in Future Bus-Based Multicore Designs.

[BibT_eX]

[DOI]

IEEE Micro, 2007

Productive and Healthy Debate.

[BibT_eX]

[DOI]

IEEE Micro, 2007

Mixing It Up.

[BibT_eX]

[DOI]

IEEE Micro, 2007

More Hot Stuff.

[BibT_eX]

[DOI]

IEEE Micro, 2007

Editor in Chief's Message: Truly "hot" chips - Do we still care?

[BibT_eX]

[DOI]

IEEE Micro, 2007

Standing on Solid Ground.

[BibT_eX]

[DOI]

IEEE Micro, 2007

Predictions of CMOS compatible on-chip optical interconnect.

[BibT_eX]

[DOI]

Integr., 2007

On-chip optical interconnect for reduced delay uncertainty.

[BibT_eX]

[DOI]

Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007

Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches.

[BibT_eX]

[DOI]

Proceedings of the High Performance Embedded Architectures and Compilers, 2007

Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006

Leveraging Optical Technology in Future Bus-based Chip Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Synergistic temperature and energy management in GALS processor architectures.

[BibT_eX]

[DOI]

Yongkang Zhu

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Localized microarchitecture-level voltage management.

[BibT_eX]

[DOI]

Yongkang Zhu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Compatible phase co-scheduling on a CMP of multi-threaded processors.

[BibT_eX]

[DOI]

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

2005

Power-Efficient Error Tolerance in Chip Multiprocessors.

[BibT_eX]

[DOI]

IEEE Micro, 2005

QUILT: a GUI-based integrated circuit floorplanning environment for computer architecture research and education.

[BibT_eX]

[DOI]

Proceedings of the 2005 workshop on Computer architecture education, 2005

A High Performance, Energy Efficient GALS ProcessorMicroarchitecture with Reduced Implementation Complexity.

[BibT_eX]

[DOI]

Yongkang Zhu

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005

Partitioning Multi-Threaded Processors with a Large Number of Threads.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005

Electrical and optical on-chip interconnects in scaled microprocessors.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Exploiting Coarse-Grain Verification Parallelism for Power-Efficient Fault Tolerance.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 2005

2004

Guest Editor's Introduction: Micro's Top Picks from Microarchitecture Conferences.

[BibT_eX]

[DOI]

IEEE Micro, 2004

An Evaluation of a Configurable Vliw Microarchitecture for Embedded Dsp Applications.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2004

Dynamically Trading Frequency for Complexity in a GALS Microprocessor.

[BibT_eX]

[DOI]

Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

Hiding Synchronization Delays in a GALS Processor Microarchitecture.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004

The Energy Impact of Aggressive Loop Fusion.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques (PACT 2004), 29 September, 2004

2003

A Dynamically Tunable Memory Hierarchy.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2003

Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor.

[BibT_eX]

[DOI]

IEEE Micro, 2003

Guest Editors' Introduction: Power and Complexity Aware Design.

[BibT_eX]

[DOI]

Pradip Bose

Diana Marculescu

IEEE Micro, 2003

Dynamically Tuning Processor Resources with Adaptive Processing.

[BibT_eX]

[DOI]

Computer, 2003

Profile-Based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor.

[BibT_eX]

[DOI]

Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

Energy Efficient Co-Adaptive Instruction Fetch and Issue.

[BibT_eX]

[DOI]

Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors.

[BibT_eX]

[DOI]

Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

Front-End Policies for Improved Issue Efficiency in SMT Processors.

[BibT_eX]

[DOI]

Ali El-Moursy

Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

Dynamic Data Dependence Tracking and its Application to Branch Prediction.

[BibT_eX]

[DOI]

Lei Chen

Steve Dropsho

Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

2002

Early-Stage Definition of LPX: A Low Power Issue-Execute Processor.

[BibT_eX]

[DOI]

Proceedings of the Power-Aware Computer Systems, Second International Workshop, 2002

Dynamic frequency and voltage control for a multiple clock domain microarchitecture.

[BibT_eX]

[DOI]

Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Managing static leakage energy in microprocessor functional units.

[BibT_eX]

[DOI]

Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

A microarchitectural-level step-power analysis tool.

[BibT_eX]

[DOI]

Wael El-Essawy

Balaram Sinharoy

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Tradeoffs in power-efficient issue queue design.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling.

[BibT_eX]

[DOI]

Greg Semeraro

Grigorios Magklis

Michael L. Scott

Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power.

[BibT_eX]

[DOI]

Steve Dropsho

Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002

2001

Reducing the complexity of the register file in dynamic superscalar processors.

[BibT_eX]

[DOI]

Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

Dynamically allocating processor resources between nearby and distant ILP.

[BibT_eX]

[DOI]

Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001

Low-Voltage 0, 25 µm CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors.

[BibT_eX]

Proceedings of the SOC Design Methodologies, 2001

A circuit level implementation of an adaptive issue queue for power-aware microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

2000

Selective Cache Ways: On-Demand Cache Resource Allocation.

[BibT_eX]

[DOI]

J. Instr. Level Parallelism, 2000

Runtime Reconfiguration Techniques for Efficient General-Purpose Computation.

[BibT_eX]

[DOI]

Bingxiong Xu

IEEE Des. Test Comput., 2000

An Adaptive Issue Queue for Reduced Power at High Performance.

[BibT_eX]

[DOI]

Proceedings of the Power-Aware Computer Systems, First International Workshop, 2000

Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures.

[BibT_eX]

[DOI]

Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000

1999

STATS: A framework for microprocessor and system-level design space exploration.

[BibT_eX]

[DOI]

J. Syst. Archit., 1999

An Architectural and Circuit-Level Approach to Improving the Energy Efficiency of Microprocessor Memory Structures.

[BibT_eX]

Proceedings of the VLSI: Systems on a Chip, 1999

1998

Dynamic IPC/Clock Rate Optimization.

[BibT_eX]

[DOI]

Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998

1997

Improving the Memory Bandwidth of Highly-Integrated, Wide-Issue, Microprocessor-Based Systems.

[BibT_eX]

[DOI]

Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), 1997

1996

A Mean Analysis Multiprocessor Model Incorporating Superscalar Processors and Latency Tolerating Techniques.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 1996

1995

Architecture and technology tradeoffs in the design of next-generation multiprocessor servers.

[BibT_eX]

[DOI]

Proceedings of the Seventh IEEE Symposium on Parallel and Distributed Processing, 1995

An analytical model of high performance superscalar-based multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, 1995

1994

Tradeoffs in the Design of Single Chip Multiprocessors.

[BibT_eX]

[DOI]