David Grant
According to our database1,
David Grant
authored at least 21 papers
between 1994 and 2021.
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Bibliography
2021
Cooling the Data Center: Design of a Mechanical Controls Owner Project Requirements (OPR) Template.
Proceedings of the IEEE International Conference on Cluster Computing, 2021
2020
Differential Codes on Higher Dimensional Varieties Via Grothendieck's Residue Symbol.
CoRR, 2020
2017
Feasibility of Single-Beam Interference Alignment in Multi-Carrier Interference Channels.
IEEE Trans. Inf. Theory, 2017
2014
2013
2012
J. Signal Process. Syst., 2012
Proceedings of the IEEE International Conference on IC Design & Technology, 2012
2011
Commun. ACM, 2011
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011
2009
A route towards production-worthy 5 µm × 25 µm and 1 µm × 20 µm non-Bosch through-silicon-via (TSV) etch, TSV metrology, and TSV integration.
Proceedings of the IEEE International Conference on 3D System Integration, 2009
Proceedings of the IEEE International Conference on 3D System Integration, 2009
2008
Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing.
ACM Trans. Reconfigurable Technol. Syst., 2008
The equivalence of space-time codes and codes defined over finite fields and Galois rings.
Adv. Math. Commun., 2008
Proceedings of the Third Workshop on Tackling Computer Systems Problems with Machine Learning Techniques, 2008
2006
Perturber: semi-synthetic circuit generation using ancestor control for testing incremental place and route.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006
Semi-Synthetic Circuit Generation Using Graph Monomorphism for Testing Incremental Placement and Incremental Routing Tools.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006
2004
A Flexible Processor for Research Prototyping.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004
1994
Design, implementation and evaluation of a high-speed integrated Hamming neural classifier.
IEEE J. Solid State Circuits, September, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994