David G. Chinnery

According to our database, David G. Chinnery authored at least 25 papers between 2000 and 2023.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2023

Introduction to the Special Section on Advances in Physical Design Automation.

Iris Hui-Ru Jiang, David G. Chinnery, Gracieli Posser, Jens Lienig

ACM Trans. Design Autom. Electr. Syst., September, 2023

Task-Based Parallel Programming for Gate Sizing.

Dimitrios Mangiras, David G. Chinnery, Giorgos Dimitrakopoulos

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023

EDA for Domain Specific Computing: An Introduction for the Panel.

Iris Hui-Ru Jiang, David G. Chinnery

Proceedings of the 2023 International Symposium on Physical Design, 2023

2022

Integrating LR Gate Sizing in an Industrial Place-and-Route Flow.

David G. Chinnery, Ankur Sharma

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

2021

Autonomous Application of Netlist Transformations Inside Lagrangian Relaxation-Based Optimization.

Apostolos Stefanidis, Dimitrios Mangiras, Chrysostomos Nicopoulos, David G. Chinnery, Giorgos Dimitrakopoulos

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

2020

Fast Lagrangian Relaxation-Based Multithreaded Gate Sizing Using Simple Timing Calibrations.

Ankur Sharma, David G. Chinnery, Tiago Reimann, Sarvesh Bhardwaj, Chris Chu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Design Optimization by Fine-grained Interleaving of Local Netlist Transformations in Lagrangian Relaxation.

Apostolos Stefanidis, Dimitrios Mangiras, Chrysostomos Nicopoulos, David G. Chinnery, Giorgos Dimitrakopoulos

Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

2019

Timing-Driven and Placement-Aware Multibit Register Composition.

Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Lagrangian Relaxation Based Gate Sizing With Clock Skew Scheduling - A Fast and Effective Approach.

Ankur Sharma, David G. Chinnery, Chris Chu

Proceedings of the 2019 International Symposium on Physical Design, 2019

Session details: Detailed Routing Contest Results.

David G. Chinnery

Proceedings of the 2019 International Symposium on Physical Design, 2019

2017

Rapid gate sizing with fewer iterations of Lagrangian Relaxation.

Ankur Sharma, David G. Chinnery, Shrirang Dhamdhere, Chris Chu

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation.

Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery

Proceedings of the 54th Annual Design Automation Conference, 2017

2015

ISPD 2015 Benchmarks with Fence Regions and Routing Blockages for Detailed-Routing-Driven Placement.

Ismail S. Bustany, David G. Chinnery, Joseph R. Shinnerl, Vladimir Yutsis

Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

Fast Lagrangian Relaxation Based Gate Sizing using Multi-Threading.

Ankur Sharma, David G. Chinnery, Sarvesh Bhardwaj, Chris C. N. Chu

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014

ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement.

Vladimir Yutsis, Ismail Bustany, David G. Chinnery, Joseph R. Shinnerl, Wen-Hao Liu

Proceedings of the International Symposium on Physical Design, 2014

2013

High performance and low power design techniques for ASIC and custom in nanometer technologies.

David G. Chinnery

Proceedings of the International Symposium on Physical Design, 2013

2007

Closing the Power Gap between ASIC and Custom - Tools and Techniques for Low Power Design.

David G. Chinnery, Kurt Keutzer

Springer, ISBN: 978-0-387-25763-1, 2007

2005

Linear programming for sizing, V_th and V_dd assignment.

David G. Chinnery, Kurt Keutzer

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Closing the power gap between ASIC and custom: an ASIC perspective.

David G. Chinnery, Kurt Keutzer

Proceedings of the 42nd Design Automation Conference, 2005

2004

Closing the Gap Between ASIC and Custom - Tools and Techniques for High-Performance ASIC Design.

David G. Chinnery, Kurt Keutzer

Springer, ISBN: 978-1-4020-7113-3, 2004

2003

Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization.

David Nguyen, Abhijit Davare, Michael Orshansky, David G. Chinnery, Brandon Thompson, Kurt Keutzer

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition.

Masayuki Ito, David G. Chinnery, Kurt Keutzer

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

2001

A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage.

Serdar Tasiran, Farzan Fallah, David G. Chinnery, Scott J. Weber, Kurt Keutzer

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Achieving 550Mhz in an ASIC Methodology.

David G. Chinnery, Borivoje Nikolic, Kurt Keutzer

Proceedings of the 38th Design Automation Conference, 2001

2000

Closing the gap between ASIC and custom: an ASIC perspective.

David G. Chinnery, Kurt Keutzer

Proceedings of the 37th Conference on Design Automation, 2000