David E. Long

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2007

Synthesis of Optimal On-Chip Baluns.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2004

Large-scale full-wave simulation.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

2002

An injection-locking scheme for precision quadrature generation.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2002

A signal integrity-driven buffer insertion technique for post-routing noise and delay optimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001

Computing Phase Noise Eigenfunctions Directly from Harmonic Balance/Shooting Matrices.

[BibT_eX]

[DOI]

Alper Demir

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

CAD for RF circuits.

[BibT_eX]

[DOI]

Piet Wambacq

Gerd Vandersteen

Joel R. Phillips

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

FILL and FUNI: algorithms to identify illegal states and sequentially untestable faults.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2000

Computing Phase Noise Eigenfunctions Directly from Steady-State Jacobian Matrices.

[BibT_eX]

[DOI]

Alper Demir

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Large-scale capacitance calculation.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

1999

Symbolic Protocol Verification with Queue BDDs.

[BibT_eX]

[DOI]

Patrice Godefroid

Formal Methods Syst. Des., 1999

Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics.

[BibT_eX]

[DOI]

Peter Feldmann

Proceedings of the 1999 Design, 1999

1998

Cyclostationary noise analysis of large RF circuits with multitone excitations.

[BibT_eX]

[DOI]

Jaijeet Roychowdhury

Peter Feldmann

IEEE J. Solid State Circuits, 1998

The design of a cache-friendly BDD library.

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

High-order Nyström schemes for efficient 3-D capacitance extraction.

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Efficient Three-Dimensional Extraction Based on Static and Full-Wave Layered Green's Functions.

[BibT_eX]

[DOI]

Proceedings of the 35th Conference on Design Automation, 1998

Tools and Methodology for RF IC Design.

[BibT_eX]

[DOI]

Proceedings of the 35th Conference on Design Automation, 1998

Efficient full-wave simulation in layered, lossy media.

[BibT_eX]

[DOI]

Jinsong Zhao

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1997

An Improved Algorithm for the Evaluation of Fixpoint Expressions.

[BibT_eX]

[DOI]

Theor. Comput. Sci., 1997

IES3: a fast integral equation solver for efficient 3-dimensional extraction.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996

Increasing testability by clock transformation (getting rid of those darn states).

[BibT_eX]

[DOI]

Krishna B. Rajan

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Model checking.

[BibT_eX]

Proceedings of the NATO Advanced Study Institute on Deductive Program Design, 1996

Efficient time-domain simulation of frequency-dependent elements.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Surprises in Sequential Redundancy Identification.

[BibT_eX]

[DOI]

Proceedings of the 1996 European Design and Test Conference, 1996

Identifying Sequential Redundancies Without Search.

[BibT_eX]

[DOI]

Vicky Hartonas-Garmhausen

Proceedings of the 33st Conference on Design Automation, 1996

1995

Verification of the Futurebus+ Cache Coherence Protocol.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 1995

Automatic verification of industrial designs.

[BibT_eX]

[DOI]

Thomas R. Kurfess

Proceedings of the Workshop on Industrial-Strength Formal Specification Techniques, 1995

Identifying sequentially untestable faults using illegal states.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

1994

Model Checking and Modular Verification.

[BibT_eX]

[DOI]

ACM Trans. Program. Lang. Syst., 1994

Model Checking and Abstraction.

[BibT_eX]

[DOI]

ACM Trans. Program. Lang. Syst., 1994

Symbolic model checking for sequential circuit verification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

1993

Verification Tools for Finite-State Concurrent Systems.

[BibT_eX]

[DOI]

Proceedings of the A Decade of Concurrency, Reflections and Perspectives, 1993

1992

PARTHENON: A Parallel Theorem Prover for Non-Horn Clauses.

[BibT_eX]

[DOI]

J. Autom. Reason., 1992

Efficient Boolean function matching.

[BibT_eX]

[DOI]

Jerry R. Burch

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1991

A language for compositional specification and verification of finite state hardware controllers.

[BibT_eX]

[DOI]

Kenneth L. McMillan

Proc. IEEE, 1991

Symbolic Model Checking with Partitioned Transistion Relations.

[BibT_eX]

Jerry R. Burch

Proceedings of the VLSI 91, 1991

Representing Circuits More Efficiently in Symbolic Model Checking.

[BibT_eX]

[DOI]

Jerry R. Burch

Proceedings of the 28th Design Automation Conference, 1991

1989

Compositional Model Checking

[BibT_eX]

[DOI]