David C. Keezer

Orcid: 0009-0002-0234-3261

Affiliations:
  • Georgia Institute of Technology, Atlanta, USA


According to our database1, David C. Keezer authored at least 65 papers between 1985 and 2024.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2010, "For contributions to high-speed digital test technology".

Timeline

Legend:

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Bibliography

2024
Multi-Stage Jitter-Reduction and Frequency Multiplication for 54 GHz ATE Clocks.
Proceedings of the IEEE International Test Conference in Asia, 2024

Characterization of Ultra-low Random Jitter Reduction Methods up to 36 GHz.
Proceedings of the IEEE European Test Symposium, 2024

2023
Experimental Evaluation of Jitter Reduction Methods for Multi-Gigahertz Test.
Proceedings of the IEEE International Test Conference in Asia, 2023

2019
Efficient Built-In Test and Calibration of High Speed Serial I/O Systems Using Monobit Signal Acquisition.
J. Electron. Test., 2019

A Framework for Design of Self-Repairing Digital Systems.
Proceedings of the IEEE International Test Conference, 2019

2018
Securing Medical Devices Against Hardware Trojan Attacks Through Analog-, Digital-, and Physiological-Based Signatures.
J. Hardw. Syst. Secur., 2018

Hardware-Based Run-Time Code Integrity in Embedded Devices.
Cryptogr., 2018

A chip-level security framework for assessing sensor data integrity: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2018

2017
Biologically inspired hierarchical structure for self-repairing FPGAs.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

Use of Analog Signatures for Hardware Trojan Detection.
Proceedings of the 14th FPGAworld Conference, 2017

2016
A 40Gbps economic extension board and FPGA-based testing platform.
Proceedings of the 21th IEEE European Test Symposium, 2016

An Ultra-High-Speed Test Module and FPGA-Based Development Platform.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
An FPGA-based ATE extension module for low-cost multi-GHz memory test.
Proceedings of the 20th IEEE European Test Symposium, 2015

A Novel Approach to Detect Hardware Trojan Attacks on Primary Data Inputs.
Proceedings of the 10th Workshop on Embedded Systems Security, 2015

2014
Multi-channel testing architecture for high-speed eye-diagram using pin electronics and subsampling monobit reconstruction algorithms.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

A signature based architecture for Trojan detection.
Proceedings of the 9th Workshop on Embedded Systems Security, 2014

2013
Practical methods for extending ATE to 40 and 50Gbps.
Proceedings of the 2013 IEEE International Test Conference, 2013

Minimizing simultaneous switching noise at reduced power with constant-voltage power transmission lines for high-speed signaling.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Enhanced Resolution Time-Domain Reflectometry for High Speed Channels: Characterizing Spatial Discontinuities with Non-ideal Stimulus.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
Guest Editorial: Special Issue on Analog, Mixed-Signal, RF, and MEMS Testing.
J. Electron. Test., 2012

Multi-gigahertz arbitrary timing generator and data pattern serializer/formatter.
Proceedings of the 2012 IEEE International Test Conference, 2012

2011
Extending a DWDM Optical Network Test System to 12 Gbps x4 Channels.
J. Electron. Test., 2011

Multi-function multi-GHz ATE extension using state-of-the-art FPGAs.
Proceedings of the 2011 IEEE International Test Conference, 2011

Two methods for 24 Gbps test signal synthesis.
Proceedings of the Design, Automation and Test in Europe, 2011

Burst-Mode Transmission and Data Recovery for Multi-GHz Optical Packet Switching Network Testing.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Low-Cost 20 Gbps Digital Test Signal Synthesis Using SiGe and InP Logic.
J. Electron. Test., 2010

An architecture for graphics processing in an FPGA (abstract only).
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Stretching the limits of FPGA SerDes for enhanced ATE performance.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
A development platform and electronic modules for automated test up to 20 Gbps.
Proceedings of the 2009 IEEE International Test Conference, 2009

2008
MEMS Switches and SiGe Logic for Multi-GHz Loopback Testing.
VLSI Design, 2008

An Electronic Module for 12.8 Gbps Multiplexing and Loopback Test.
Proceedings of the 2008 IEEE International Test Conference, 2008

Variable Delay of Multi-Gigahertz Digital Signals for Deskew and Jitter-Injection Test Applications.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Multi-GHz loopback testing using MEMs switches and SiGe logic.
Proceedings of the 2007 IEEE International Test Conference, 2007

Co-development of test electronics and PCI Express interface for a multi-Gbps optical switching network.
Proceedings of the 2007 IEEE International Test Conference, 2007

Method for reducing jitter in multi-gigahertz ATE.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Source-Synchronous Testing of Multilane PCI Express and HyperTransport Buses.
IEEE Des. Test Comput., 2006

Multi-Gigahertz Testing of Wafer-Level Packaged Devices.
Proceedings of the 2006 IEEE International Test Conference, 2006

2005
Implementing multi-gigahertz test systems using CMOS FPGAs and PECL components.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL.
Proceedings of the 2005 Design, 2005

A 5 Gbps Wafer-Level Tester.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
Multiplexing ATE Channels for Production Testing at 2.5 Gbps.
IEEE Des. Test Comput., 2004

Modular Extension of ATE to 5 Gbps.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
A Production-Oriented Multiplexing System for Testing above 2.5 Gbps.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Application and Demonstration of a Digital Test Core: Optoelectronic Test Bed and Wafer-level Prober.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002
Multi-GigaHertz Testing Challenges and Solutions.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Challenges and Solutions for Multi-Gigahertz Testing.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Multi-Purpose Digital Test Core Utilizing Programmable Logic.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001
Terabit-per-second automated digital testing.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

1999
Test support processors for enhanced testability of high performance circuits.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998
A high throughput test methodology for MCM substrates.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Alternative interface methods for testing high speed bidirectional signals.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Improved sensitivity for parallel test of substrate interconnections.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997
A Low-Cost Massively-Parallel Interconnect Test Method for MCM Substrates.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Low-Cost ATE PinElectronics for Multigigabit-per-Second At-Speed Test.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1995
Electrical Troubleshooting, Diagnostics, and Repair of Multichip Modules.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1993
Known Godd Die for MCMs: Enabling Technologies.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

SMAC: A Scene Matching Chip.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

1992
An Architecture for WSI Rapid Prototyping.
Computer, 1992

Calibration Techniques for a Gigahertz Test System.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

MCM Test Using Available Technology.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991
Wafer Scale Integration: A university perspective.
J. VLSI Signal Process., 1991

Real-Time Data Comparison for GigaHertz Digital Test.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

High Frequency Wafer Probing and Power Supply Resonance Effects.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990
Multiplexing test system channels for data rates above 1 Gb/s.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1985
Tester Independent Support Software System (TISSS).
Proceedings of the Proceedings International Test Conference 1985, 1985


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