David Biancolin

Orcid: 0000-0001-6371-9053

According to our database1, David Biancolin authored at least 11 papers between 2016 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Simulator Independent Coverage for RTL Hardware Languages.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2021
Accessible, FPGA Resource-Optimized Simulation of Multiclock Systems in FireSim.
IEEE Micro, 2021

2020
Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs.
IEEE Micro, 2020

Invited: Chipyard - An Integrated SoC Research and Implementation Environment.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud.
IEEE Micro, 2019

Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes.
Proceedings of the International Conference on Computer-Aided Design, 2019

FASED: FPGA-Accelerated Simulation and Evaluation of DRAM.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018
DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of Cycles.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017
A Hardware Accelerator for Computing an Exact Dot Product.
Proceedings of the 24th IEEE Symposium on Computer Arithmetic, 2017

2016
Fine-Grained Interconnect Synthesis.
ACM Trans. Reconfigurable Technol. Syst., 2016

JITPCB.
Proceedings of the 2016 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2016


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