David B. Whalley

Proceedings of the 24th ACM SIGPLAN/SIGBED International Conference on Languages, 2023

Facilitating the Bootstrapping of a New ISA.

[BibT_eX]

[DOI]

Proceedings of the 24th ACM SIGPLAN/SIGBED International Conference on Languages, 2023

2022

Experience with Integrating Computer Science in Middle School Mathematics.

[BibT_eX]

[DOI]

Sherry A. Southerland

Christine Andrews-Larson

Ellen Granger

Proceedings of the ITiCSE 2022: Innovation and Technology in Computer Science Education, Dublin, Ireland, July 8, 2022

2021

Decreasing the Miss Rate and Eliminating the Performance Penalty of a Data Filter Cache.

[BibT_eX]

[DOI]

Michael Stokes

Soner Önder

ACM Trans. Archit. Code Optim., 2021

The domestic computer science graduate students are there, we just need to recruit them.

[BibT_eX]

[DOI]

Xiuwen Liu

Commun. ACM, 2021

2020

Experience of Administering Our First S-STEM Program to Broaden Participation in Computer Science.

[BibT_eX]

[DOI]

Proceedings of the 51st ACM Technical Symposium on Computer Science Education, 2020

2019

Improving Energy Efficiency by Memoizing Data Access Information.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

2018

Decoupling address generation from loads and stores to improve data access energy efficiency.

[BibT_eX]

[DOI]

Proceedings of the 19th ACM SIGPLAN/SIGBED International Conference on Languages, 2018

2016

Practical way halting by speculatively accessing halt tags.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Remix: On-demand Live Randomization.

[BibT_eX]

[DOI]

Proceedings of the Sixth ACM on Conference on Data and Application Security and Privacy, 2016

Redesigning a tagless access buffer to require minimal ISA changes.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Compilers, 2016

2015

Improving Data Access Efficiency by Using Context-Aware Loads and Stores.

[BibT_eX]

[DOI]

Proceedings of the 16th ACM SIGPLAN/SIGBED Conference on Languages, 2015

Optimizing Transfers of Control in the Static Pipeline Architecture.

[BibT_eX]

[DOI]

Proceedings of the 16th ACM SIGPLAN/SIGBED Conference on Languages, 2015

Scheduling instruction effects for a statically pipelined processor.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Compilers, 2015

2014

A journey toward obtaining our first NSF S-STEM (scholarship) grant.

[BibT_eX]

[DOI]

Proceedings of the 45th ACM Technical Symposium on Computer Science Education, 2014

Energy efficient data access techniques.

[BibT_eX]

[DOI]

Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2014

Reducing set-associative L1 data cache energy by early load data dependence detection (ELD<sup>3</sup>).

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Reducing instruction fetch energy in multi-issue processors.

[BibT_eX]

[DOI]

Peter Gavin

Magnus Själander

ACM Trans. Archit. Code Optim., 2013

Designing a practical data filter cache to improve both energy efficiency and performance.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2013

Improving processor efficiency by statically pipelining instructions.

[BibT_eX]

[DOI]

Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2013

Speculative tag access for reduced energy dissipation in set-associative L1 data caches.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Improving data access efficiency by using a tagless access buffer (TAB).

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization, 2013

2012

Program Differentiation.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2012

An Overview of Static Pipelining.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2012

2011

Improving Low Power Processor Efficiency with Static Pipelining.

[BibT_eX]

[DOI]

Proceedings of the 15th Workshop on Interaction between Compilers and Computer Architectures, 2011

2010

Parametric timing analysis and its application to dynamic voltage scaling.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2010

Improving both the performance benefits and speed of optimization phase sequence searches.

[BibT_eX]

[DOI]

Prasad A. Kulkarni

Michael R. Jantz

Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, 2010

2009

Introduction.

[BibT_eX]

[DOI]

Per Stenström

Trans. High Perform. Embed. Archit. Compil., 2009

Practical exhaustive optimization phase order exploration and evaluation.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2009

Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE).

[BibT_eX]

[DOI]

Stephen Roderick Hines

Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, 2009

2008

The worst-case execution-time problem - overview of methods and survey of tools.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2008

Enhancing the effectiveness of utilizing an instruction register file.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

2007

Guest Editorial.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2007

Fast, accurate design space exploration of embedded systems memory configurations.

[BibT_eX]

[DOI]

Jason Hiser

Proceedings of the 2007 ACM Symposium on Applied Computing (SAC), 2007

Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache.

[BibT_eX]

[DOI]

Stephen Hines

Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

Addressing instruction fetch bottlenecks by using an instruction register file.

[BibT_eX]

[DOI]

Stephen Roderick Hines

Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, 2007

Generalizing parametric timing analysis.

[BibT_eX]

[DOI]

Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, 2007

Evaluating Heuristic Optimization Phase Order Search Algorithms.

[BibT_eX]

[DOI]

Prasad A. Kulkarni

Proceedings of the Fifth International Symposium on Code Generation and Optimization (CGO 2007), 2007

Facilitating compiler optimizations through the dynamic mapping of alternate register structures.

[BibT_eX]

[DOI]

Christopher Zimmer

Stephen Roderick Hines

Prasad A. Kulkarni

Proceedings of the 2007 International Conference on Compilers, 2007

2006

VISTA: VPO interactive system for tuning applications.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2006

Improving WCET by applying worst-case path optimizations.

[BibT_eX]

[DOI]

Real Time Syst., 2006

In search of near-optimal optimization phase orderings.

[BibT_eX]

[DOI]

Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Languages, 2006

Reducing the cost of conditional transfers of control by using comparison specifications.

[BibT_eX]

[DOI]

Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Languages, 2006

On the Use of Compilers in DSP Laboratory Instruction.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

Exhaustive Optimization Phase Order Space Exploration.

[BibT_eX]

[DOI]

Proceedings of the Fourth IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2006), 2006

Adapting compilation techniques to enhance the packing of instructions into registers.

[BibT_eX]

[DOI]

Stephen Hines

Proceedings of the 2006 International Conference on Compilers, 2006

2005

Improving WCET by applying a WC code-positioning optimization.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2005

Fast and efficient searches for effective optimization-phase sequences.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2005

Compiler transformations for effectively exploiting a zero overhead loop buffer.

[BibT_eX]

[DOI]

Softw. Pract. Exp., 2005

Branch elimination by condition merging.

[BibT_eX]

[DOI]

Softw. Pract. Exp., 2005

ParaScale: Exploiting Parametric Timing Analysis for Real-Time Schedulers and Dynamic Voltage Scaling.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Real-Time Systems Symposium (RTSS 2005), 2005

Improving WCET by Optimizing Worst-Case Paths.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2005), 2005

Timing Analysis for Sensor Network Nodes of the Atmega Processor Family.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2005), 2005

Reducing Instruction Fetch Cost by Packing Instructions into RegisterWindows.

[BibT_eX]

[DOI]

Stephen Hines

Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 2005

Improving Program Efficiency by Packing Instructions into Registers.

[BibT_eX]

[DOI]

Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

Tuning High Performance Kernels through Empirical Compilation.

[BibT_eX]

[DOI]

R. Clint Whaley

Proceedings of the 34th International Conference on Parallel Processing (ICPP 2005), 2005

Using de-optimization to re-optimize code.

[BibT_eX]

[DOI]

Proceedings of the EMSOFT 2005, 2005

2004

Fast memory bank assignment for fixed-point digital signal processors.

[BibT_eX]

[DOI]

Jeonghun Cho

Yunheung Paek

ACM Trans. Design Autom. Electr. Syst., 2004

Automatic validation of code-improving transformations on low-level program representations.

[BibT_eX]

[DOI]

Robert van Engelen

Sci. Comput. Program., 2004

WCET Code Positioning.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Real-Time Systems Symposium (RTSS 2004), 2004

Tuning the WCET of Embedded Applications.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2004), 2004

Fast searches for effective optimization phase sequences.

[BibT_eX]

[DOI]

Proceedings of the ACM SIGPLAN 2004 Conference on Programming Language Design and Implementation 2004, 2004

2003

Industrial Requirements for WCET Tools - Answers to the ARTIST Questionnaire.

[BibT_eX]

Proceedings of the 3rd International Workshop on Worst-Case Execution Time Analysis, 2003

Validation of Code-Improving Transformations for Embedded Systems.

[BibT_eX]

[DOI]

Robert van Engelen

Proceedings of the 2003 ACM Symposium on Applied Computing (SAC), 2003

Finding effective optimization phase sequences.

[BibT_eX]

[DOI]

Proceedings of the 2003 Conference on Languages, 2003

Branch Elimination via Multi-variable Condition Merging.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2003. Parallel Processing, 2003

2002

Automatic Detection and Exploitation of Branch Constraints for Timing Analysis.

[BibT_eX]

[DOI]

Christopher A. Healy

IEEE Trans. Software Eng., 2002

Efficient and effective branch reordering using profile data.

[BibT_eX]

[DOI]

Minghui Yang

ACM Trans. Program. Lang. Syst., 2002

VISTA: a system for interactive code improvement.

[BibT_eX]

[DOI]

Proceedings of the 2002 Joint Conference on Languages, 2002

Efficient register and memory assignment for non-orthogonal architectures via graph coloring and MST algorithms.

[BibT_eX]

[DOI]

Jeonghun Cho

Yunheung Paek

Proceedings of the 2002 Joint Conference on Languages, 2002

2001

Improving Memory Hierarchy Performance for Irregular Applications Using Data and Computation Reorderings.

[BibT_eX]

[DOI]

Ken Kennedy

Int. J. Parallel Program., 2001

On providing useful information for analyzing and tuning applications.

[BibT_eX]

[DOI]

Robert J. Fowler

Proceedings of the Joint International Conference on Measurements and Modeling of Computer Systems, 2001

Parametric Timing Analysis.

[BibT_eX]

[DOI]

Proceedings of the 2001 ACM SIGPLAN Workshop on Optimization of Middleware and Distributed Systems, 2001

Tools for application-oriented performance tuning.

[BibT_eX]

[DOI]

Robert J. Fowler

Proceedings of the 15th international conference on Supercomputing, 2001

Using a Swap Instruction to Coalesce Loads and Stores.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2001: Parallel Processing, 2001

2000

Supporting Timing Analysis by Automatic Bounding of Loop Iterations.

[BibT_eX]

[DOI]

Real Time Syst., 2000

Automatic Validation of Code-Improving Transformations.

[BibT_eX]

[DOI]

Robert van Engelen

Proceedings of the Languages, 2000

Techniques for Effectively Exploiting a Zero Overhead Loop Buffer.

[BibT_eX]

[DOI]

Proceedings of the Compiler Construction, 9th International Conference, 2000

1999

Bounding Pipeline and Instruction Cache Performance.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1999

Effectively Exploiting Indirect Jumps.

[BibT_eX]

[DOI]

Softw. Pract. Exp., 1999

Timing Constraint Specification and Analysis.

[BibT_eX]

[DOI]

Softw. Pract. Exp., 1999

Timing Analysis for Data and Wrap-Around Fill Caches.

[BibT_eX]

[DOI]

Real Time Syst., 1999

Tighter Timing Predictions by Automatic Detection and Exploitation of Value-Dependent Constraints.

[BibT_eX]

[DOI]

Christopher A. Healy

Proceedings of the Fifth IEEE Real-Time Technology and Applications Symposium, 1999

Effective Exploitation of a Zero Overhead Loop Buffer.

[BibT_eX]

[DOI]

Proceedings of the ACM SIGPLAN 1999 Workshop on Languages, 1999

Improving memory hierarchy performance for irregular applications.

[BibT_eX]

[DOI]

Ken Kennedy

Proceedings of the 13th international conference on Supercomputing, 1999

1998

Bounding Loop Iterations for Timing Analysis.

[BibT_eX]

[DOI]

Proceedings of the Fourth IEEE Real-Time Technology and Applications Symposium, 1998

Improving Performance by Branch Reordering.

[BibT_eX]

[DOI]

Minghui Yang

Proceedings of the ACM SIGPLAN '98 Conference on Programming Language Design and Implementation (PLDI), 1998

Decreasing Process Memory Requirements by Overlapping Program Portions.

[BibT_eX]

[DOI]

Richard L. Bowman

Emily Ratliff

Proceedings of the Thirty-First Annual Hawaii International Conference on System Sciences, 1998

1997

Coalescing Conditional Branches into Efficient Indirect Jumps.

[BibT_eX]

[DOI]

Proceedings of the Static Analysis, 4th International Symposium, 1997

Timing Analysis for Data Caches and Set-Associative Caches.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE Real-Time Technology and Applications Symposium, 1997

1996

Supporting the specification and analysis of timing constraints.

[BibT_eX]

[DOI]

Proceedings of the 2nd IEEE Real-Time Technology and Applications Symposium, 1996

1995

Fast context switches: compiler and architectural support for preemptive scheduling.

[BibT_eX]

[DOI]

Jeffrey S. Snyder

Theodore P. Baker

Microprocess. Microsystems, 1995

Graphical visualization of compiler optimizations.

[BibT_eX]

[DOI]

Mickey R. Boyd

J. Program. Lang., 1995

Integrating the Timing Analysis of Pipelining and Instruction Caching.

[BibT_eX]

[DOI]

Christopher A. Healy

Proceedings of the 16th IEEE Real-Time Systems Symposium, 1995

Avoiding Conditional Branches by Code Replication.

[BibT_eX]

[DOI]

Proceedings of the ACM SIGPLAN'95 Conference on Programming Language Design and Implementation (PLDI), 1995

Supporting User-Friendly Analysis of Timing Constraints.

[BibT_eX]

[DOI]

Lo Ko

Proceedings of the ACM SIGPLAN 1995 Workshop on Languages, 1995

Appropriate Interfaces Between Design Tools, Languages, Compilers and Runtimes in Real-Time Systems (Panel).

[BibT_eX]

[DOI]

Proceedings of the ACM SIGPLAN 1995 Workshop on Languages, 1995

Fast instruction cache analysis via static cache simulation.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 28st Annual Simulation Symposium (SS '95), 1995

1994

Automatic Isolation of Compiler Errors.

[BibT_eX]

[DOI]

ACM Trans. Program. Lang. Syst., 1994

A Retargetable Technique for Predicting Execution Time of Code Segments.

[BibT_eX]

[DOI]

Theodore P. Baker

Real Time Syst., 1994

Efficient On-the-fly Analysis of Program Behavior and Static Cache Simulation.

[BibT_eX]

[DOI]

Proceedings of the Static Analysis, First International Static Analysis Symposium, 1994

Bounding Worst-Case Instruction Cache Performance.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE Real-Time Systems Symposium (RTSS '94), 1994

Real-Time Debugging by Minimal Hardware Simulation.

[BibT_eX]

[DOI]

Proceedings of the PEARL 94, 1994

1993

Techniques for Fast Instruction Cache Performance Evaluation.

[BibT_eX]

[DOI]

Softw. Pract. Exp., 1993

Isolation and Analysis of Optimization Errors.

[BibT_eX]

[DOI]

Mickey R. Boyd

Proceedings of the ACM SIGPLAN'93 Conference on Programming Language Design and Implementation (PLDI), 1993

1992

Relating Static and Dynamic Machine Code Measurements.

[BibT_eX]

[DOI]

John R. Rabung

IEEE Trans. Computers, 1992

Fast Instruction Cache Performance Evaluation Using Compile-Time Analysis.

[BibT_eX]

[DOI]

Proceedings of the 1992 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems, 1992

A Retargetable Technique for Predicting Execution Time.

[BibT_eX]

[DOI]

Theodore P. Baker

Proceedings of the Real-Time Systems Symposium, 1992

Avoiding Unconditional Jumps by Code Replication.

[BibT_eX]

[DOI]

Proceedings of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation (PLDI), 1992

1991

Methods for Saving and Restoring Register Values across Function Calls.

[BibT_eX]

[DOI]

Softw. Pract. Exp., 1991

A design environment for addressing architecture and compiler interactions.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 1991

1990

Ease: An Environment for Architecture Study and Experimentation.

[BibT_eX]

[DOI]

Proceedings of the 1990 ACM SIGMETRICS conference on Measurement and modeling of computer systems, 1990

Reducing the Cost of Branches by Using Registers.

[BibT_eX]

[DOI]

Proceedings of the 17th Annual International Symposium on Computer Architecture, 1990

1989

Quick Compilers Using Peephole Optimization.

[BibT_eX]

[DOI]