David B. Thomas

Proceedings of the International Conference on Field-Programmable Technology, 2020

Termination detection for fine-grained message-passing architectures.

[BibT_eX]

[DOI]

A. Theodore Markettos

Thomas Bytheway

Andrew D. Brown

Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020

2019

POETS: Distributed Event-Based Computing - Scaling Behaviour.

[BibT_eX]

[DOI]

Proceedings of the Parallel Computing: Technology Trends, 2019

Tinsel: A Manythread Overlay for FPGA Clusters.

[BibT_eX]

[DOI]

Matthew Naylor

Simon W. Moore

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Accelerating Position-Aware Top-k ListNet for Ranking Under Custom Precision Regimes.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Templatised Soft Floating-Point for High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Formalizing Loop-Carried Dependencies in Coq for High-Level Synthesis.

[BibT_eX]

[DOI]

Florian Faissole

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Compile-Time Generation of Custom-Precision Floating-Point IP using HLS Tools.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019

2018

A High-Level Design Framework for the Automatic Generation of High-Throughput Systolic Binomial-Tree Solvers.

[BibT_eX]

[DOI]

Aryan Tavakkoli

IEEE Trans. Very Large Scale Integr. Syst., 2018

Accelerating Top-k ListNet Training for Ranking Using FPGA.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2018

Injecting FPGA Configuration Faults in Parallel.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2018

Redundancy-Reduced MobileNet Acceleration on Reconfigurable Logic for ImageNet Classification.

[BibT_eX]

[DOI]

Peter Y. K. Cheung

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic.

[BibT_eX]

[DOI]

Peter Y. K. Cheung

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017

A Domain Specific Approach to High Performance Heterogeneous Computing.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2017

Distributed Event-Based Computing.

[BibT_eX]

[DOI]

Alessandro de Gennaro

Andrey Mokhov

Matthew Naylor

Tom Kazmierski

Proceedings of the Parallel Computing is Everywhere, 2017

Programming Model to Develop Supercomputer Combinatorial Solvers.

[BibT_eX]

[DOI]

Proceedings of the 46th International Conference on Parallel Processing Workshops, 2017

Using Runahead Execution to Hide Memory Latency in High Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

2016

Neural Network Based Reinforcement Learning Acceleration on FPGA Platforms.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2016

AT-GIS: Highly Parallel Spatial Query Processing with Associative Transducers.

[BibT_eX]

[DOI]

Peter Ogden

Peter R. Pietzuch

Proceedings of the 2016 International Conference on Management of Data, 2016

SynADT: Dynamic Data Structures in High Level Synthesis.

[BibT_eX]

[DOI]

Zeping Xue

Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

Increasing Network Size and Training Throughput of FPGA Restricted Boltzmann Machines Using Dropout.

[BibT_eX]

[DOI]

Jiang Su

Peter Y. K. Cheung

Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

StitchUp: automatic control flow protection for high level synthesis circuits.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

Synthesisable recursion for C++ HLS tools.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015

The Table-Hadamard GRNG: An Area-Efficient FPGA Gaussian Random Number Generator.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2015

Parallel Genetic Algorithms on Multiple FPGAs.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2015

A Toolchain for Dynamic Function Off-load on CPU-FPGA Platforms.

[BibT_eX]

[DOI]

J. Inf. Process., 2015

Courier: A Toolchain for Application Acceleration on Heterogeneous Platforms.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2015

A general-purpose framework for FPGA-accelerated genetic algorithms.

[BibT_eX]

[DOI]

Int. J. Bio Inspired Comput., 2015

An Efficient, Automatic Approach to High Performance Heterogeneous Computing.

[BibT_eX]

[DOI]

CoRR, 2015

Seeing Shapes in Clouds: On the Performance-Cost trade-off for Heterogeneous Infrastructure-as-a-Service.

[BibT_eX]

[DOI]

CoRR, 2015

SysAlloc: A hardware manager for dynamic memory allocation in heterogeneous systems.

[BibT_eX]

[DOI]

Zeping Xue

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Recursive pipelined genetic propagation for bilevel optimisation.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

PushPush: Seamless integration of hardware and software objects via function calls over AXI.

[BibT_eX]

[DOI]

Ivan Beretta

Dan R. Ghica

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System.

[BibT_eX]

[DOI]

Dan R. Ghica

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Pipelined Genetic Propagation.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Transparent linking of compiled software and synthesized hardware.

[BibT_eX]

[DOI]

Dan R. Ghica

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A General-Purpose Method for Faithfully Rounded Floating-Point Function Approximation in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE Symposium on Computer Arithmetic, 2015

2014

An Automatic Mixed Software Hardware Pipeline Builder for CPU-FPGA Platforms.

[BibT_eX]

[DOI]

CoRR, 2014

A Domain Specific Approach to Heterogeneous Computing: From Availability to Accessibility.

[BibT_eX]

[DOI]

CoRR, 2014

Low-latency option pricing using systolic binomial trees.

[BibT_eX]

[DOI]

Aryan Tavakkoli

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Is high level synthesis ready for business? A computational finance case study.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Automated framework for FPGA-based parallel genetic algorithms.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Area implications of memory partitioning for high-level synthesis on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Heterogeneous Heartbeats: A framework for dynamic management of Autonomous SoCs.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

FPGA Gaussian Random Number Generators with Guaranteed Statistical Accuracy.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Compiling Higher Order Functional Programs to Composable Digital Hardware.

[BibT_eX]

[DOI]

Eduardo Aguilar-Pelaez

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Automated Framework for General-Purpose Genetic Algorithms in FPGAs.

[BibT_eX]

[DOI]

Liucheng Guo

Proceedings of the Applications of Evolutionary Computation - 17th European Conference, 2014

2013

Multiplierless Algorithm for Multivariate Gaussian Random Number Generation in FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Customisable architectures for the set covering problem.

[BibT_eX]

[DOI]

Liucheng Guo

SIGARCH Comput. Archit. News, 2013

Scalable XML Query Processing using Parallel Pushdown Transducers.

[BibT_eX]

[DOI]

Peter Ogden

Peter R. Pietzuch

Proc. VLDB Endow., 2013

A Heterogeneous Computing Framework for Computational Finance.

[BibT_eX]

[DOI]

Proceedings of the 42nd International Conference on Parallel Processing, 2013

A fully pipelined FPGA architecture for stochastic simulation of chemical systems.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

FPGA based control for real time systems.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Parallel Generation of Gaussian Random Numbers Using the Table-Hadamard Transform.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Hardware Acceleration of Matrix Multiplication over Small Prime Finite Fields.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2012

Design Exploration of Quadrature Methods in Option Pricing.

[BibT_eX]

[DOI]

Anson H. T. Tse

IEEE Trans. Very Large Scale Integr. Syst., 2012

A Domain Specific Language and Toolchain for OpenCV Runtime Binary Acceleration Using GPU.

[BibT_eX]

[DOI]

Proceedings of the Third International Conference on Networking and Computing, 2012

Optimising explicit finite difference option pricing for dynamic constant reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Exploring the latency-resource trade-off for the Discrete Fourier Transform on the FPGA.

[BibT_eX]

[DOI]

Simon Winberg

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Parallel FPGA-based all pairs shortest paths for sparse networks: A human brain connectome case study.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

A mixed precision Monte Carlo methodology for reconfigurable accelerator systems.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

A Reconfigurable Computing Approach for Efficient and Scalable Parallel Graph Exploration.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

Optimising Performance of Quadrature Methods with Reduced Precision.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

Multi-level Customisation Framework for Curve Based Monte Carlo Financial Simulations.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011

Management and programming of reconfigurable hardware resources.

[BibT_eX]

[DOI]

PhD thesis, 2011

A framework for FPGA acceleration of large graph problems: Graphlet counting case study.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Unifying Finite Difference Option-Pricing for Hardware Acceleration.

[BibT_eX]

[DOI]

Qiwei Jin

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

On Comparing Financial Option Price Solvers on FPGA.

[BibT_eX]

[DOI]

Qiwei Jin

Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

2010

Efficient reconfigurable design for pricing asian options.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2010

Dynamic scheduling Monte-Carlo framework for multi-accelerator heterogeneous clusters.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2010

Comparing performance and energy efficiency of FPGAs and GPUs for high productivity computing.

[BibT_eX]

[DOI]

Brahim Betkaoui

Proceedings of the International Conference on Field-Programmable Technology, 2010

Reconfigurable Control Variate Monte-Carlo Designs for Pricing Exotic Options.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

An FPGA-specific algorithm for direct generation of multi-variate Gaussian random numbers.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009

Exploring Reconfigurable Architectures for Tree-Based Option Pricing Models.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2009

FPGA Accelerated Low-Latency Market Data Feed Processing.

[BibT_eX]

[DOI]

Gareth W. Morris

Proceedings of the 17th IEEE Symposium on High Performance Interconnects, 2009

Exploring reconfigurable architectures for explicit finite difference option pricing models.

[BibT_eX]

[DOI]

Qiwei Jin

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation.

[BibT_eX]

[DOI]

Lee W. Howes

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Accelerating Quadrature Methods for Option Valuation.

[BibT_eX]

[DOI]

Anson H. T. Tse

Proceedings of the FCCM 2009, 2009

FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the FCCM 2009, 2009

2008

Multivariate Gaussian Random Number Generation Targeting Reconfigurable Hardware.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2008

Estimation of sample mean and variance for Monte-Carlo simulations.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Sampling from the exponential distribution using independent Bernoulli variates.

[BibT_eX]

[DOI]

Proceedings of the FPL 2008, 2008

FPGA-optimised high-quality uniform random number generators.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

Credit Risk Modelling using Hardware Accelerated Monte-Carlo Simulation.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

Resource efficient generators for the floating-point uniform and exponential distributions.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2008

An FPGA run-time parameterisable Log-Normal Random Number Generator.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2008

2007

High Quality Uniform Random Number Generation Using LUT Optimised State-transition Matrices.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2007

Non-uniform random number generation through piecewise linear approximations.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2007

Gaussian random number generators.

[BibT_eX]

[DOI]

John D. Villasenor

ACM Comput. Surv., 2007

A Domain Specific Language for Reconfigurable Path-based Monte Carlo Simulations.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Sampling from the Multivariate Gaussian Distribution using Reconfigurable Hardware.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

Automatic Generation and Optimisation of Reconfigurable Financial Monte-Carlo Simulations.

[BibT_eX]

[DOI]

Jacob A. Bower

Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

Reconfigurable Hardware Acceleration of Canonical Graph Labelling.

[BibT_eX]

[DOI]

Michael Stumpf

Proceedings of the Reconfigurable Computing: Architectures, 2007

2006

A Reconfigurable Simulation Framework for Financial Computation.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006

Hardware architectures for Monte-Carlo based financial simulations.

[BibT_eX]

[DOI]

Jacob A. Bower

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Efficient Hardware Generation of Random Variates with Arbitrary Distributions.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

2005

High quality uniform random number generation for massively parallel simulations in FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs, 2005

High Quality Uniform Random Number Generation Through LUT Optimised Linear Recurrences.

[BibT_eX]

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

2004

Pipelining designs with loop-carried dependencies.

[BibT_eX]

[DOI]

Henry Styles

Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Implementing Graphics Shaders Using FPGAs.

[BibT_eX]

[DOI]