David A. Yokoyama-Martin

According to our database1, David A. Yokoyama-Martin authored at least 4 papers between 2002 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

2005
2010
2015
2020
2025
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1
2
1
1
1
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Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2025
A 224 Gb/s 3 pJ/bit 40 dB Insertion Loss Transceiver in 3-nm FinFET CMOS.
IEEE J. Solid State Circuits, January, 2025

2006
A Multi-Standard Low Power 1.5-3.125 Gb/s Serial Transceiver in 90nm CMOS.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
A multigigabit backplane transceiver core in 0.13-μm CMOS with a power-efficient equalization architecture.
IEEE J. Solid State Circuits, 2005

2002
An adaptive PAM-4 5 Gb/s backplane transceiver in 0.25 μm CMOS.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002


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