Dave Bradley

According to our database, Dave Bradley authored at least 4 papers between 2009 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2018

A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS.

Shenggao Li, Fulvio Spagna, Ji Chen, Xiaoqing Wang, Luke Tong, Sujatha Gowder, Wenyan Jia, Roan Nicholson, Sitaraman Iyer, Rui Song, Lily Li, Meng-hung Chen, Amanda Tran, Michael De Vita, Deepar Govindrajan, Marcus Pasquarella, Dave Bradley, Frank Verdico, Matt Duwe, Eric Lee, Michelle Wigton

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2016

The Xeon® Processor E5-2600 v3: a 22 nm 18-Core Product Family.

William J. Bowhill, Blaine A. Stackhouse, Nevine Nassif, Zibing Yang, Arvind Raghavan, Oscar Mendoza, Charles Morganti, Chris Houghton, Dan Krueger, Olivier Franza, Jayen Desai, Jason Crop, Brian Brock, Dave Bradley, Chris Bostak, Sal Bhimji, Matt Becker

IEEE J. Solid State Circuits, 2016

2015

4.5 The Xeon® processor E5-2600 v3: A 22nm 18-core product family.

William J. Bowhill, Blaine A. Stackhouse, Nevine Nassif, Zibing Yang, Arvind Raghavan, Charles Morganti, Chris Houghton, Dan Krueger, Olivier Franza, Jayen Desai, Jason Crop, Dave Bradley, Chris Bostak, Sal Bhimji, Matt Becker

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2009

A 65 nm 2-Billion Transistor Quad-Core Itanium Processor.

Blaine A. Stackhouse, Sal Bhimji, Chris Bostak, Dave Bradley, Brian S. Cherkauer, Jayen Desai, Erin Francom, Mike Gowan, Paul E. Gronowski, Dan Krueger, Charles Morganti, Steve Troyer

IEEE J. Solid State Circuits, 2009