Dashan Shang

Orcid: 0000-0003-3573-8390

According to our database1, Dashan Shang authored at least 25 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Fully Binarized Graph Convolutional Network Accelerator Based on In-Memory Computing with Resistive Random-Access Memory.
Adv. Intell. Syst., July, 2024

2T2R RRAM-Based In-Memory Hyperdimensional Computing Encoder for Spatio-Temporal Signal Processing.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2024

Topology Optimization of Random Memristors for Input-Aware Dynamic SNN.
CoRR, 2024

Dynamic neural network with memristive CIM and CAM for 2D and 3D vision.
CoRR, 2024

Older and Wiser: The Marriage of Device Aging and Intellectual Property Protection of Deep Neural Networks.
CoRR, 2024

Continuous-Time Digital Twin with Analogue Memristive Neural Ordinary Differential Equation Solver.
CoRR, 2024

Efficient and accurate neural field reconstruction using resistive memory.
CoRR, 2024

Resistive Memory-based Neural Differential Equation Solver for Score-based Diffusion Model.
CoRR, 2024

Older and Wiser: The Marriage of Device Aging and Intellectual Property Protection of DNNs.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference.
IEEE J. Solid State Circuits, October, 2023

A Scalable Small-Footprint Time-Space-Pipelined Architecture for Reservoir Computing.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

An ADC-Less RRAM-Based Computing-in-Memory Macro With Binary CNN for Efficient Edge AI.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

Echo state graph neural networks with analogue random resistive memory arrays.
Nat. Mac. Intell., February, 2023

Random resistive memory-based deep extreme point learning machine for unified visual processing.
CoRR, 2023

Pruning random resistive memory for optimizing analogue AI.
CoRR, 2023

Resistive memory-based zero-shot liquid state machine for multimodal event data learning.
CoRR, 2023

2022
Convolutional Echo-State Network with Random Memristors for Spatiotemporal Signal Classification.
Adv. Intell. Syst., 2022

Mixed-Precision Continual Learning Based on Computational Resistance Random Access Memory.
Adv. Intell. Syst., 2022

Few-shot graph learning with robust and energy-efficient memory-augmented graph neural network (MAGNN) based on homogeneous computing-in-memory.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

3D Reservoir Computing with High Area Efficiency (5.12 TOPS/mm<sup>2</sup>) Implemented by 3D Dynamic Memristor Array for Temporal Signal Processing.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
Efficient and Robust Nonvolatile Computing-In-Memory Based on Voltage Division in 2T2R RRAM With Input-Dependent Sensing Control.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Anti-Sway and Positioning Adaptive Control of a Double-Pendulum Effect Crane System With Neural Network Compensation.
Frontiers Robotics AI, 2021

Echo state graph neural networks with analogue random resistor arrays.
CoRR, 2021

2020
Ion-Gated Transistor: An Enabler for Sensing and Computing Integration.
Adv. Intell. Syst., 2020

2016
Nonvolatile Multi-level Memory and Boolean Logic Gates Based on a Single Memtranstor.
CoRR, 2016


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