Darlene Viviani
According to our database1,
Darlene Viviani
authored at least 2 papers
between 2016 and 2017.
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Bibliography
2017
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017
2016
Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory.
IEEE J. Solid State Circuits, 2016