Darío Suárez Gracia

Diana Göhringer

J. Syst. Archit., 2022

Efficient Semantic Segmentation with Hyperspectral Images.

[BibT_eX]

[DOI]

Proceedings of the ROBOT 2022: Fifth Iberian Robotics Conference, 2022

peRISCVcope: A Tiny Teaching-Oriented RISC-V Interpreter.

[BibT_eX]

[DOI]

Alejandro Valero

Maria Angélica Dávila-Guzmán

Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022

2021

On the use of many-core Marvell ThunderX2 processor for HPC workloads.

[BibT_eX]

[DOI]

J. Supercomput., 2021

Analytical Model for Memory-Centric High Level Synthesis-Generated Applications.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2021

A learning experience toward the understanding of abstraction-level interactions in parallel applications.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2021

RRCD: Redirección de Registros Basada en Compresión de Datos para Tolerar FallosPermanentes en una GPU.

[BibT_eX]

[DOI]

CoRR, 2021

2020

Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform.

[BibT_eX]

[DOI]

J. Supercomput., 2020

Analytical Model of Memory-Bound Applications Compiled with High Level Synthesis.

[BibT_eX]

[DOI]

CoRR, 2020

DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files.

[BibT_eX]

[DOI]

Alejandro Valero

IEEE Access, 2020

An Analytical Model of Memory-Bound Applications Compiled with High Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2019

Correction to: Simultaneous multiprocessing in a software-defined heterogeneous FPGA.

[BibT_eX]

[DOI]

Sam Amiri

J. Supercomput., 2019

Simultaneous multiprocessing in a software-defined heterogeneous FPGA.

[BibT_eX]

[DOI]

Sam Amiri

J. Supercomput., 2019

Cooperative CPU, GPU, and FPGA heterogeneous execution with EngineCL.

[BibT_eX]

[DOI]

Raúl Nozal

José Luis Bosque

J. Supercomput., 2019

An Aging-Aware GPU Register File Design Based on Data Redundancy.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

Exploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs.

[BibT_eX]

[DOI]

J. Syst. Archit., 2019

A fault-tolerant last level cache for CMPs operating at ultra-low voltage.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2019

Exposing Abstraction-Level Interactions with a Parallel Ray Tracer.

[BibT_eX]

[DOI]

Agustín Navarro-Torres

Proceedings of the Workshop on Computer Architecture Education, 2019

2018

AISC: Approximate Instruction Set Computer.

[BibT_eX]

[DOI]

Alexandra Ferreron

Ulya R. Karpuzcu

CoRR, 2018

Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems.

[BibT_eX]

[DOI]

CoRR, 2018

Towards the Inclusion of FPGAs on Commodity Heterogeneous Systems.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018

2017

Exploiting Data Compression to Mitigate Aging in GPU Register Files.

[BibT_eX]

[DOI]

Proceedings of the 29th International Symposium on Computer Architecture and High Performance Computing, 2017

Simultaneous Multiprocessing on a FPGA+CPU Heterogeneous System-On-Chip.

[BibT_eX]

[DOI]

Proceedings of the Parallel Computing is Everywhere, 2017

Abstract Representation of Shared Data for Heterogeneous Computing.

[BibT_eX]

[DOI]

Proceedings of the Languages and Compilers for Parallel Computing, 2017

2016

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage.

[BibT_eX]

[DOI]

Pablo Ibáñez

IEEE Trans. Computers, 2016

Analysis of network-on-chip topologies for cost-efficient chip multiprocessors.

[BibT_eX]

[DOI]

Marta Ortín-Obón

Microprocess. Microsystems, 2016

Reactive circuits: Dynamic construction of circuits for reactive traffic in homogeneous CMPs.

[BibT_eX]

[DOI]

Marta Ortín-Obón

J. Parallel Distributed Comput., 2016

2015

Concurrency in Mobile Browser Engines.

[BibT_eX]

[DOI]

Calin Cascaval

Pablo Montesinos-Ortego

Behnam Robatmili

IEEE Pervasive Comput., 2015

2014

Revisiting LP-NUCA Energy Consumption: Cache Access Policies and Adaptive Block Dropping.

[BibT_eX]

[DOI]

Luis Montesano Del Campo

ACM Trans. Archit. Code Optim., 2014

Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

Dynamic construction of circuits for reactive traffic in homogeneous CMPs.

[BibT_eX]

[DOI]

Marta Ortín

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Characterization and cost-efficient selection of NoC topologies for general purpose CMPs.

[BibT_eX]

[DOI]

Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip, 2013

Shrinking L1 Instruction Caches to Improve Energy-Delay in SMT Embedded Processors.

[BibT_eX]

[DOI]

Marta Ortín-Obón

Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013

2012

LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors.

[BibT_eX]

[DOI]

Giorgos Dimitrakopoulos

Manolis Katevenis

IEEE Trans. Very Large Scale Integr. Syst., 2012

Automatic discovery of performance and energy pitfalls in HTML and CSS.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Workload Characterization, 2012

2009

SigRace: signature-based data race detection.

[BibT_eX]

[DOI]

Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Light NUCA: A proposal for bridging the inter-cache latency gap.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2007

A proposal to introduce power and energy notions in computer architecture laboratories.

[BibT_eX]

[DOI]

Alicia Asín Pérez