Dara Rahmati

Orcid: 0000-0003-0104-4016

According to our database1, Dara Rahmati authored at least 37 papers between 2006 and 2024.

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Bibliography

2024
Enhancing Computational Efficiency in Intensive Domains via Redundant Residue Number Systems.
CoRR, 2024

GELU-MSDF: A Hardware Accelerator for Transformer's GELU Activation Function Using Most Significant Digit First Computation.
Proceedings of the 37th IEEE International System-on-Chip Conference, 2024

Enhancing Efficiency in Computational Intensive Domains via Redundant Residue Number Systems.
Proceedings of the 21st International SoC Design Conference, 2024

2023
FPGA-orthopoly: a hardware implementation of orthogonal polynomials.
Eng. Comput., 2023

Deep Perspective Transformation Based Vehicle Localization on Bird's Eye View.
CoRR, 2023

2022
A multi-application approach for synthesizing custom network-on-chips.
J. Supercomput., 2022

HyperDbg: Reinventing Hardware-Assisted Debugging.
CoRR, 2022

Hardware Efficient FIR Filter Architectures Using Accurate Unary Stochastic Computing.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

HyperDbg: Reinventing Hardware-Assisted Debugging.
Proceedings of the 2022 ACM SIGSAC Conference on Computer and Communications Security, 2022

2021
A High-throughput Parallel Viterbi Algorithm via Bitslicing.
ACM Trans. Parallel Comput., 2021

An energy efficient synthesis flow for application specific SoC design.
Integr., 2021

High-Performance Deterministic Stochastic Computing Using Residue Number System.
IEEE Des. Test, 2021

Unlucky Explorer: A Complete non-Overlapping Map Exploration.
Proceedings of the WSSE 2021: The 3rd World Symposium on Software Engineering, Xiamen, China, September 24, 2021

On Using Monte-Carlo Tree Search to Solve Puzzles.
Proceedings of the ICCTA 2021: 7th International Conference on Computer Technology Applications, Vienna, Austria, July 13, 2021

A TSX-Based KASLR Break: Bypassing UMIP and Descriptor-Table Exiting.
Proceedings of the Risks and Security of Internet and Systems, 2021

2020
Traffic-aware performance optimization in Real-time wireless network on chip.
Nano Commun. Networks, 2020

Unlucky Explorer: A Complete non-Overlapping Map Exploration.
CoRR, 2020

A Way Around UMIP and Descriptor-Table Exiting via TSX-based Side-Channel Attack.
CoRR, 2020

On the Resilience of Deep Learning for Reduced-voltage FPGAs.
Proceedings of the 28th Euromicro International Conference on Parallel, 2020

TaxoNN: A Light-Weight Accelerator for Deep Neural Network Training.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

BSRNG: A High Throughput Parallel BitSliced Approach for Random Number Generators.
Proceedings of the ICPP Workshops '20: Workshops, Edmonton, AB, Canada, August 17-20, 2020, 2020

2019
Decentralized Cooperative Communication-less Multi-Agent Task Assignment with Monte-Carlo Tree Search.
CoRR, 2019

High-performance Cryptographically Secure Pseudo-random Number Generation via Bitslicing.
CoRR, 2019

SkippyNN: An Embedded Stochastic-Computing Accelerator for Convolutional Neural Networks.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Multi-Agent non-Overlapping Pathfinding with Monte-Carlo Tree Search.
Proceedings of the IEEE Conference on Games, 2019

Using Residue Number Systems to Accelerate Deterministic Bit-stream Multiplication.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018
Classified Round Robin: A Simple Prioritized Arbitration to Equip Best Effort NoCs With Effective Hard QoS.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

High-Average and Guaranteed Performance for Wireless Networks-on-Chip Architectures.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Accurate Performance Bounds Calculation for Dynamic Voltage-Freq Islands in Best Effort NoCs.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

2013
Designing best effort networks-on-chip to meet hard latency constraints.
ACM Trans. Embed. Comput. Syst., 2013

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip.
IEEE Trans. Computers, 2013

2012
Power-efficient deterministic and adaptive routing in torus networks-on-chip.
Microprocess. Microsystems, 2012

2009
A method for calculating hard QoS guarantees for Networks-on-Chip.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008
A Markovian Performance Model for Networks-on-Chip.
Proceedings of the 16th Euromicro International Conference on Parallel, 2008

An Adaptive Approach to Manage the Number of Virtual Channels.
Proceedings of the 22nd International Conference on Advanced Information Networking and Applications, 2008

2007
Effect of number of faults on NoC power and performance.
Proceedings of the 13th International Conference on Parallel and Distributed Systems, 2007

2006
A performance and power analysis of WK-Recursive and Mesh Networks for Network-on-Chips.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006


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