Danilo Vendraminetto
Orcid: 0000-0002-5321-6513
According to our database1,
Danilo Vendraminetto
authored at least 12 papers
between 2013 and 2020.
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Bibliography
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Model Checking Speculation-Dependent Security Properties: Abstracting and Reducing Processor Models for Sound and Complete Verification.
Proceedings of the Codes, Cryptology and Information Security, 2019
2017
IEEE Des. Test, 2017
Interpolation-Based Learning as a Mean to Speed-Up Bounded Model Checking (Short Paper).
Proceedings of the Software Engineering and Formal Methods - 15th International Conference, 2017
2016
Proceedings of the 1st IEEE International Verification and Security Workshop, 2016
Proceedings of the 2016 Formal Methods in Computer-Aided Design, 2016
2015
Optimization techniques for craig interpolant compaction in unbounded model checking.
Formal Methods Syst. Des., 2015
2014
Hardware Model Checking Competition 2014: An Analysis and Comparison of Solvers and Benchmarks.
J. Satisf. Boolean Model. Comput., 2014
Tightening BDD-based approximate reachability with SAT-based clause generalization<sup>∗</sup>.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Fast cone-of-influence computation and estimation in problems with multiple properties.
Proceedings of the Design, Automation and Test in Europe, 2013