Daniele Gardellini

According to our database¹, Daniele Gardellini authored at least 5 papers between 2012 and 2014.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Bibliography

2014

A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2014

2012

A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2012

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2012

A 28Gb/s source-series terminated TX in 32nm CMOS SOI.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Daniele Gardellini

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