Daniele Bortolotti

Orcid: 0000-0002-2175-2418

According to our database1, Daniele Bortolotti authored at least 21 papers between 2011 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2018
Energy-Aware Bio-Signal Compressed Sensing Reconstruction on the WBSN-Gateway.
IEEE Trans. Emerg. Top. Comput., 2018

2017
A Synchronization-Based Hybrid-Memory Multi-Core Architecture for Energy-Efficient Biomedical Signal Processing.
IEEE Trans. Computers, 2017

Energy Analysis of Decoders for Rakeness-Based Compressed Sensing of ECG Signals.
IEEE Trans. Biomed. Circuits Syst., 2017

Zeroing for HW-efficient compressed sensing architectures targeting data compression in wireless sensor networks.
Microprocess. Microsystems, 2017

2016
VirtualSoC: A Research Tool for Modern MPSoCs.
ACM Trans. Embed. Comput. Syst., 2016

User-space APIs for dynamic power management in many-core ARMv8 computing nodes.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016

Quantifying the benefits of compressed sensing on a WBSN-based real-time biosignal monitor.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

PHIDIAS: ultra-low-power holistic design for smart bio-signals computing platforms.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Application of compressed sensing to ECG signals: Decoder-side benefits of the rakeness approach.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

2015
Long-Term ECG monitoring with zeroing Compressed Sensing approach.
Proceedings of the Nordic Circuits and Systems Conference, 2015

Energy-Aware Bio-signal Compressed Sensing Reconstruction: FOCUSS on the WBSN-Gateway.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

An ultra-low power dual-mode ECG monitor for healthcare and wellness.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
An ultra-low power resilient multi-core architecture with static and dynamic tolerance to ambient temperature-induced variability.
Microprocess. Microsystems, 2014

Approximate compressed sensing: ultra-low power biosignal processing via aggressive voltage scaling on a hybrid memory multi-core processor.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Hybrid memory architecture for voltage scaling in ultra-low power multi-core biomedical processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Rakeness-based compressed sensing on ultra-low power multi-core biomedicai processors.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

2013
A variation tolerant architecture for ultra low power multi-processor cluster.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

VirtualSoC: A Full-System Simulation Environment for Massively Parallel Heterogeneous System-on-Chip.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

An Ambient Temperature Variation Tolerance Scheme for an Ultra Low Power Shared-L1 Processor Cluster.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Exploring instruction caching strategies for tightly-coupled shared-memory clusters.
Proceedings of the 2011 International Symposium on System on Chip, 2011


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