Daniel Yingling
According to our database1,
Daniel Yingling
authored at least 6 papers
between 2015 and 2024.
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Bibliography
2024
14.3 A 3nm Adaptive Clock Duty-Cycle Controller for Mitigating Aging-Induced Clock Duty-Cycle Distortion.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2019
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 7nm All-Digital Unified Voltage and Frequency Regulator Based on a High-Bandwidth 2-Phase Buck Converter with Package Inductors.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
2016
A 16 nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range.
IEEE J. Solid State Circuits, 2016
2015
8.5 A 16nm auto-calibrating dynamically adaptive clock distribution for maximizing supply-voltage-droop tolerance across a wide operating range.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015