Daniel Thiele
According to our database1,
Daniel Thiele
authored at least 16 papers
between 2012 and 2022.
Collaborative distances:
Collaborative distances:
Timeline
2012
2014
2016
2018
2020
2022
0
1
2
3
4
5
6
1
1
1
4
2
3
1
2
1
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2022
Formal Timing Analysis of Ethernet TSN Extensions for Automotive Applications (Formale Timing Analyse von Ethernet TSN Erweiterungen für automobile Anwendungen)
PhD thesis, 2022
2017
Proceedings of the Handbook of Hardware/Software Codesign., 2017
A system-level FPGA design methodology for video applications with weakly-programmable hardware components.
J. Real Time Image Process., 2017
2016
Real Time Syst., 2016
Formal worst-case performance analysis of time-sensitive Ethernet with frame preemption.
Proceedings of the 21st IEEE International Conference on Emerging Technologies and Factory Automation, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Formal analysis based evaluation of software defined networking for time-sensitive Ethernet.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
Formal worst-case timing analysis of Ethernet TSN's time-aware and peristaltic shapers.
Proceedings of the 2015 IEEE Vehicular Networking Conference, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
2014
Proceedings of the 9th IEEE International Symposium on Industrial Embedded Systems, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Improving formal timing analysis of switched ethernet by exploiting traffic stream correlations.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014
2013
Improved formal worst-case timing analysis of weighted round robin scheduling for Ethernet.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013
2012
Formal worst-case timing analysis of Ethernet topologies with strict-priority and AVB switching.
Proceedings of the 7th IEEE International Symposium on Industrial Embedded Systems, 2012
Optimizing performance analysis for synchronous dataflow graphs with shared resources.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012