Daniel Sánchez

According to our database, Daniel Sánchez authored at least 9 papers between 2009 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

Soft-error mitigation by means of decoupled transactional memory threads.

Daniel Sánchez, Juan M. Cebrian, José M. García, Juan L. Aragón

Distributed Comput., 2015

2014

Managing power constraints in a single-core scenario through power tokens.

Juan M. Cebrian, Daniel Sánchez, Juan L. Aragón, Stefanos Kaxiras

J. Supercomput., 2014

2013

Modeling the impact of permanent faults in caches.

Daniel Sánchez, Yiannakis Sazeides, Juan M. Cebrian, José M. García, Juan L. Aragón

ACM Trans. Archit. Code Optim., 2013

Efficient inter-core power and thermal balancing for multicore processors.

Juan M. Cebrian, Daniel Sánchez, Juan L. Aragón, Stefanos Kaxiras

Computing, 2013

2012

A fault-tolerant architecture for parallel applications in tiled-CMPs.

Daniel Sánchez, Juan L. Aragón, José M. García

J. Supercomput., 2012

2011

An analytical model for the calculation of the Expected Miss Ratio in faulty caches.

Daniel Sánchez, Yiannakis Sazeides, Juan L. Aragón, José M. García

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

2010

A log-based redundant architecture for reliable parallel computation.

Daniel Sánchez, Juan L. Aragón, José M. García

Proceedings of the 2010 International Conference on High Performance Computing, 2010

2009

Extending SRT for parallel applications in tiled-CMP architectures.

Daniel Sánchez, Juan L. Aragón, José M. García

Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

REPAS: Reliable Execution for Parallel ApplicationS in Tiled-CMPs.

Daniel Sánchez, Juan L. Aragón, José M. García

Proceedings of the Euro-Par 2009 Parallel Processing, 2009