Daniel Pollex

According to our database, Daniel Pollex authored at least 5 papers between 2006 and 2011.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2011

A 56GS/S 6b DAC in 65nm CMOS with 256×6b memory.

Yuriy M. Greshishchev, Daniel Pollex, Shing-Chi Wang, Marinette Besson, Philip Flemeke, Stefan Szilagyi, Jorge Aguirre, Chris Falt, Naim Ben-Hamida, Robert Gibbins, Peter Schvan

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010

A 40GS/s 6b ADC in 65nm CMOS.

Yuriy M. Greshishchev, Jorge Aguirre, Marinette Besson, Robert Gibbins, Chris Falt, Philip Flemke, Naim Ben-Hamida, Daniel Pollex, Peter Schvan, Shing-Chi Wang

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

Clock recovery for a 40 Gb/s QPSK optical receiver.

Naim Ben-Hamida, John Sitch, Philip Flemke, Daniel Pollex, Peter Schvan, Yuriy M. Greshishchev, Shing-Chi Wang, Chris Falt

Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008

A 24GS/s 6b ADC in 90nm CMOS.

Peter Schvan, Jérôme Bach, Chris Falt, Philip Flemke, Robert Gibbins, Yuriy M. Greshishchev, Naim Ben-Hamida, Daniel Pollex, John Sitch, Shing-Chi Wang, John Wolczanski

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2006

A 22GS/s 5b adc in 0.13µm SiGe BiCMOS.

Peter Schvan, Daniel Pollex, Shing-Chi Wang, Chris Falt, Naim Ben-Hamida

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006