Daniel Petrisko

Orcid: 0000-0002-0555-6919

According to our database1, Daniel Petrisko authored at least 11 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Scaling Program Synthesis Based Technology Mapping with Equality Saturation.
CoRR, 2024

Scalable, Programmable and Dense: The HammerBlade Open-Source RISC-V Manycore.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

2023
RISE: RISC-V SoC for En/Decryption Acceleration on the Edge for Homomorphic Encryption.
IEEE Trans. Very Large Scale Integr. Syst., October, 2023

2022
The BlackParrot BedRock Cache Coherence System.
CoRR, 2022

RACE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Computation.
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

2020
Design Space Exploration for Chiplet-Assembly-Based Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2020

BlackParrot: An Agile Open-Source RISC-V Multicore for Accelerator SoCs.
IEEE Micro, 2020

NoC Symbiosis : (Special Session Paper).
Proceedings of the 14th IEEE/ACM International Symposium on Networks-on-Chip, 2020

2019
Architecting Waferscale Processors - A GPU Case Study.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

2018
A Case for Packageless Processors.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2016
Rescuing Uncorrectable Fault Patterns in On-Chip Memories through Error Pattern Transformation.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016


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