Daniel Mozos

Orcid: 0000-0003-1867-3310

According to our database1, Daniel Mozos authored at least 70 papers between 1991 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A Real-Time FPGA Implementation of the LCMV Algorithm for Target Classification in Hyperspectral Images Using LDL Decomposition.
IEEE Trans. Geosci. Remote. Sens., 2024

Parametric Pipelined k-Means Implementation for Hyperspectral Processing on Spacecraft Embedded FPGA.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2024

2023
Real-Time Independent Components Analysis for Dimensional Reduction of Hyperspectral Images Using Reconfigurable Hardware.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

2022
A Real-Time FPGA Implementation of the CCSDS 123.0-B-2 Standard.
IEEE Trans. Geosci. Remote. Sens., 2022

2020
An Extremely Pipelined FPGA Implementation of a Lossy Hyperspectral Image Compression Algorithm.
IEEE Trans. Geosci. Remote. Sens., 2020

An FPGA Accelerator for Real-Time Lossy Compression of Hyperspectral Images.
Remote. Sens., 2020

2019
Noise estimation for hyperspectral subspace identification on FPGAs.
J. Supercomput., 2019

FPGA implementation of the principal component analysis algorithm for dimensionality reduction of hyperspectral images.
J. Real Time Image Process., 2019

2018
FPGA Implementation of the CCSDS 1.2.3 Standard for Real-Time Hyperspectral Lossless Compression.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2018

Hyperspectral Image Compression Using Vector Quantization, PCA and JPEG2000.
Remote. Sens., 2018

A novel FPGA-based architecture for the estimation of the virtual dimensionality in remotely sensed hyperspectral images.
J. Real Time Image Process., 2018

2017
Parallel Implementation of the CCSDS 1.2.3 Standard for Hyperspectral Lossless Compression.
Remote. Sens., 2017

2016
FPGA Implementation of an Algorithm for Automatically Detecting Targets in Remotely Sensed Hyperspectral Images.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2016

Dimensionality reduction of hyperspectral images using reconfigurable hardware.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015
FPGA Implementation of the HySime Algorithm for the Determination of the Number of Endmembers in Hyperspectral Data.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2015

FPGA implementation to estimate the number of endmembers in hyperspectral images.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

2014
Configuration Mapping Algorithms to Reduce Energy and Time Reconfiguration Overheads in Reconfigurable Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2014

An approach to manage reconfigurations and reduce area cost in hard real-time reconfigurable systems.
ACM Trans. Embed. Comput. Syst., 2014

A performance/cost model for a CUDA drug discovery application on physical and public cloud infrastructures.
Concurr. Comput. Pract. Exp., 2014

2013
The Promise of Reconfigurable Computing for Hyperspectral Imaging Onboard Systems: A Review and Trends.
Proc. IEEE, 2013

Use of FPGA or GPU-based architectures for remotely sensed hyperspectral image processing.
Integr., 2013

2012
FPGA Implementation of the N-FINDR Algorithm for Remotely Sensed Hyperspectral Image Analysis.
IEEE Trans. Geosci. Remote. Sens., 2012

FPGA Implementation of Abundance Estimation for Spectral Unmixing of Hyperspectral Data Using the Image Space Reconstruction Algorithm.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2012

2011
A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A Replacement Technique to Maximize Task Reuse in Reconfigurable Systems.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

2010
A task graph execution manager for reconfigurable multi-tasking systems.
Microprocess. Microsystems, 2010

FPGA Implementation of the Pixel Purity Index Algorithm for Remotely Sensed Hyperspectral Image Analysis.
EURASIP J. Adv. Signal Process., 2010

A Constant Complexity Allocation Algorithm for Reconfigurable Systems Management Adapted to Heterogeneous Workload Profiles.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

FPGA for Computing the Pixel Purity Index Algorithm on Hyperspectral Images.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

2009
3D FPGA resource management and fragmentation metric for hardware multitasking.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

FPGA support for satellite computations of hyper spectral images.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008
Efficiently scheduling runtime reconfigurations.
ACM Trans. Design Autom. Electr. Syst., 2008

Allocation heuristics and defragmentation measures for reconfigurable systems management.
Integr., 2008

Constant complexity scheduling for hardware multitasking in two dimensional reconfigurable field-programmable gate arrays.
IET Comput. Digit. Tech., 2008

A Hardware Task-Graph Scheduler for Reconfigurable Multi-tasking Systems.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Perimeter quadrature-based metric for estimating FPGA fragmentation in 2D HW multitasking.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Pull vs. Hybrid: Comparing Scheduling Algorithms for Asymmetric Time-Constrained Environments.
Proceedings of the 2008 International Conference on Wireless Networks, 2008

Resource Management for Hw Multitasking in Three Dimensional FPGAs.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

FPGA Resource Management Using Internal RAM as Aata Cache.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

Synthesis of relocatable tasks and implementation of a task communication bus in a general purpose Hw system.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

2007
Memory hierarchy for high-performance and energyaware reconfigurable systems.
IET Comput. Digit. Tech., 2007

HW implementation of an execution manager for reconfigurable systems.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

Reducing the reconfiguration overhead: a survey of techniques.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

2006
2D defragmentation heuristics for hardware multitasking on reconfigurable devices.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

A configuration memory hierarchy for fast reconfiguration with reduced energy consumption overhead.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Adaptive Hybrid Broadcast for Data Dissemination in Time-Constrained Asymmetric Communication Environments.
Proceedings of the 32nd EUROMICRO Conference on Software Engineering and Advanced Applications (EUROMICRO-SEAA 2006), August 29, 2006

Partition Based Dynamic 2D HW Multitasking Management.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Task placement heuristic based on 3D-adjacency and look-ahead in reconfigurable systems.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005
A Reconfiguration Manager for Dynamically Reconfigurable Hardware.
IEEE Des. Test Comput., 2005

A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware.
Proceedings of the 2005 Design, 2005

2004
A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs.
Microprocess. Microsystems, 2004

New Alternatives to the Estimation Problem in Hardware-Software Codesign of Complex Embedded Systems: The H.261 Video Co-dec Case Study.
Des. Autom. Embed. Syst., 2004

A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management.
Proceedings of the Field Programmable Logic and Application, 2004

Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware.
Proceedings of the 41th Design Automation Conference, 2004

2003
Analyzing communication overheads during hardware/software partitioning.
Microelectron. J., 2003

A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements.
Proceedings of the Integrated Circuit and System Design, 2003

Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Application of Task Concurrency Management on Dynamically Reconfigurable Hardware Platforms.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

Run-Time Scheduling for Multimedia Applications on Dynamically Reconfigurable Systems.
Proceedings of the First Workshop on Embedded Systems for Real-Time Multimedia, 2003

1999
The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach.
Proceedings of the 1999 Design, 1999

1998
A Grouping Partitioning Technique with Automatic Criterion Selection for the Codesign Proces.
Proceedings of the 24th EUROMICRO '98 Conference, 1998

A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process.
Proceedings of the 1998 Design, 1998

1994
Clock cycle estimation based on dead time and control unit area minimization.
Microprocess. Microprogramming, 1994

1993
Data path structures and heuristics for testable allocation in high level synthesis.
Microprocess. Microprogramming, 1993

Guidance for optimization-based synthesis tools.
Microprocess. Microprogramming, 1993

Global hardware synthesis guided by realistic probability computation.
Microprocess. Microprogramming, 1993

1992
Design control in a high level synthesis system.
Microprocess. Microprogramming, 1992

Heuristics for branch-and-bound global allocation.
Proceedings of the conference on European design automation, 1992

1991
A hardware allocator guided by cost functions.
Microprocessing and Microprogramming, 1991


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