Daniel M. Dreps
According to our database1,
Daniel M. Dreps
authored at least 27 papers
between 2007 and 2022.
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Bibliography
2022
POWER10™: A 16-Core SMT8 Server Processor With 2TB/s Off-Chip Bandwidth in 7nm Technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2020
A 25×50Gb/s 2.22pJ/b NRZ RX with Dual-Bank and 3-Tap Speculative DFE for Microprocessor Application in 7nm FinFET CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4.
IEEE J. Solid State Circuits, 2018
IBM J. Res. Dev., 2018
2017
Contutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processor.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2015
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.
IEEE J. Solid State Circuits, 2015
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
5.1 POWER8<sup>TM</sup>: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
The POWER8<sup>TM</sup> processor: Designed for big data, analytics, and cloud environments.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014
2012
IEEE J. Solid State Circuits, 2012
2011
IEEE J. Solid State Circuits, 2011
2010
A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS.
IEEE J. Solid State Circuits, 2010
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
The IBM POWER7 HUB module: A terabyte interconnect switch for high-performance computer systems.
Proceedings of the 2010 IEEE Hot Chips 22 Symposium, Stanford, CA, USA, August 22-24, 2010, 2010
2009
IBM J. Res. Dev., 2009
A 5.4mW 0.0035mm<sup>2</sup> 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Design methodology of high performance on-chip global interconnect using terminated transmission-line.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 2008
Proceedings of the 45th Design Automation Conference, 2008
2007
IBM J. Res. Dev., 2007