Daniel Kehrer

According to our database, Daniel Kehrer authored at least 11 papers between 2001 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2010

A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques.

Rex Kho, David Boursin, Martin Brox, Peter Gregorius, Heinz Hoenigschmid, Bianka Kho, Sabine Kieser, Daniel Kehrer, Maksim Kuzmenka, Udo Moeller, Pavel Veselinov Petkov, Manfred Plan, Michael Richter, Ian Russell, Kai Schiller, Ronny Schneider, Kartik Swaminathan, Bradley Weber, Julien Weber, Ingo Bormann, Fabien Funfrock, Mario Gjukic, Wolfgang Spirkl, Holger Steffens, Jörg Weller, Thomas Hein

IEEE J. Solid State Circuits, 2010

2009

75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques.

Rex Kho, David Boursin, Martin Brox, Peter Gregorius, Heinz Hoenigschmid, Bianka Kho, Sabine Kieser, Daniel Kehrer, Maksim Kuzmenka, Udo Moeller, Pavel Veselinov Petkov, Manfred Plan, Michael Richter, Ian Russell, Kai Schiller, Ronny Schneider, Kartik Swaminathan, Bradley Weber, Julien Weber, Ingo Bormann, Fabien Funfrock, Mario Gjukic, Wolfgang Spirkl, Holger Steffens, Jörg Weller, Thomas Hein

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2007

Cascading Techniques for a High-Speed Memory Interface.

Zheng Gu, Peter Gregorius, Daniel Kehrer, Lydia Neumann, Evelyn Neuscheler, Thomas Rickes, Hermann Ruckerbauer, Ralf Schledz, Martin Streibl, Jürgen Zielbauer

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005

A 24 GHz dual-modulus prescaler in 90nm CMOS.

Hans-Dieter Wohlmuth, Daniel Kehrer

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

A 30-gb/s 70-mW one-stage 4: 1 multiplexer in 0.13-μm CMOS.

Daniel Kehrer, Hans-Dieter Wohlmuth

IEEE J. Solid State Circuits, 2004

A low power 13-Gb/s 2^7-1 pseudo random bit sequence generator IC in 120 nm bulk CMOS.

Hans-Dieter Wohlmuth, Daniel Kehrer

Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

2003

40-Gb/s 2: 1 multiplexer and 1: 2 demultiplexer in 120-nm standard CMOS.

Daniel Kehrer, Hans-Dieter Wohlmuth, Herbert Knapp, Martin Wurzer, Arpad L. Scholtz

IEEE J. Solid State Circuits, 2003

A 15 GHz 256/257 dual-modulus prescaler in 120 nm CMOS.

Hans-Dieter Wohlmuth, Daniel Kehrer

Proceedings of the ESSCIRC 2003, 2003

A 20 Gb/s 82mW one-stage 4:1 multiplexer in 0.13 μm CMOS.

Daniel Kehrer, Hans-Dieter Wohlmuth

Proceedings of the ESSCIRC 2003, 2003

2002

A monolithic 2.45 GHz, 0.56 W power amplifier with 45% PAE at 2.4 V in standard 25 GHz f_T Si-bipolar.

Winfried Bakalski, Werner Simbürger, Daniel Kehrer, Hans-Dieter Wohlmuth, Mirjana Rest, Arpad L. Scholtz

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001

Modeling of monolithic lumped planar transformers up to 20 GHz.

Daniel Kehrer, Werner Simbürger, Hans-Dieter Wohlmuth, Arpad L. Scholtz

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001