Daniel J. Sorin

According to our database, Daniel J. Sorin authored at least 106 papers between 1998 and 2024.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

2024

Low-Energy Line Codes for On-Chip Networks.

Beyza Dabak, Major Glenn, Jingyang Liu, Alexander Buck, Siyi Yang, A. Robert Calderbank, Natalie Enright Jerger, Daniel J. Sorin

CoRR, 2024

Determining the Minimum Number of Virtual Networks for Different Coherence Protocols.

Weihang Li, Andrés Goens, Nicolai Oswald, Vijay Nagarajan, Daniel J. Sorin

Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

PipeGen: Automated Transformation of a Single-Core Pipeline into a Multicore Pipeline for a Given Memory Consistency Model.

An Qi Zhang, Andrés Goens, Nicolai Oswald, Tobias Grosser, Daniel J. Sorin, Vijay Nagarajan

Proceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques, 2024

2023

HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols.

Nicolai Oswald, Vijay Nagarajan, Daniel J. Sorin, Vasilis Gavrielatos, Theo X. Olausson, Reece Carr

IEEE Micro, 2023

Rigorous Evaluation of Computer Processors with Statistical Model Checking.

Filip Mazurek, Arya Tschand, Yu Wang, Miroslav Pajic, Daniel J. Sorin

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

2022

Spatiotemporal Strategies for Long-Term FPGA Resource Management.

Atefeh Mehrabi, Daniel J. Sorin, Benjamin C. Lee

Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

2021

Bayesian Optimization for Efficient Accelerator Synthesis.

Atefeh Mehrabi, Aninda Manocha, Benjamin C. Lee, Daniel J. Sorin

ACM Trans. Archit. Code Optim., 2021

Reconfigurable Hardware in Postsilicon Microarchitecture.

Daniel J. Sorin

Computer, 2021

Learning Sparse Matrix Row Permutations for Efficient SpMM on GPU Architectures.

Atefeh Mehrabi, Donghyuk Lee, Niladrish Chatterjee, Daniel J. Sorin, Benjamin C. Lee, Mike O'Connor

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021

2020

A Primer on Memory Consistency and Cache Coherence, Second Edition

Vijay Nagarajan, Daniel J. Sorin, Mark D. Hill, David A. Wood

Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01764-3, 2020

Computer Architecture for Orbital Edge Computing.

Daniel J. Sorin

Computer, 2020

HieraGen: Automated Generation of Concurrent, Hierarchical Cache Coherence Protocols.

Nicolai Oswald, Vijay Nagarajan, Daniel J. Sorin

Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Roadmap Subsampling for Changing Environments.

Sean Murray, George Dimitri Konidaris, Daniel J. Sorin

Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2020

Foosball Coding: Correcting Shift Errors and Bit Flip Errors in 3D Racetrack Memory.

Samantha Archer, Georgios Mappouras, A. Robert Calderbank, Daniel J. Sorin

Proceedings of the 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2020

Prospector: Synthesizing Efficient Accelerators via Statistical Learning.

Atefeh Mehrabi, Aninda Manocha, Benjamin C. Lee, Daniel J. Sorin

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

GreenFlag: Protecting 3D-Racetrack Memory from Shift Errors.

Georgios Mappouras, Alireza Vahid, A. Robert Calderbank, Daniel J. Sorin

Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019

A Programmable Architecture for Robot Motion Planning Acceleration.

Sean Murray, Will Floyd-Jones, George Dimitri Konidaris, Daniel J. Sorin

Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018

Extending Flash Lifetime in Embedded Processors by Expanding Analog Choice.

Georgios Mappouras, Alireza Vahid, A. Robert Calderbank, Daniel J. Sorin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Low-Power Content Addressable Memory.

Daniel J. Sorin

Computer, 2018

ProtoGen: Automatically Generating Directory Cache Coherence Protocols from Atomic Specifications.

Nicolai Oswald, Vijay Nagarajan, Daniel J. Sorin

Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

2017

Correcting Two Deletions and Insertions in Racetrack Memory.

Alireza Vahid, Georgios Mappouras, Daniel J. Sorin, A. Robert Calderbank

CoRR, 2017

Persistent Memory.

Daniel J. Sorin

Computer, 2017

Architecting hierarchical coherence protocols for push-button parametric verification.

Opeoluwa Matthews, Daniel J. Sorin

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Jenga: Efficient Fault Tolerance for Stacked DRAM.

Georgios Mappouras, Alireza Vahid, A. Robert Calderbank, Derek R. Hower, Daniel J. Sorin

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2016

Top Picks from the 2015 Computer Architecture Conferences.

Milo M. K. Martin, Daniel J. Sorin

IEEE Micro, 2016

Profile-Driven Automated Mixed Precision.

Ralph Nathan, Helia Naeimi, Daniel J. Sorin, Xiaobai Sun

CoRR, 2016

TREES: A CPU/GPU Task-Parallel Runtime with Explicit Epoch Synchronization.

Blake A. Hechtman, Andrew D. Hilton, Daniel J. Sorin

CoRR, 2016

Robot Motion Planning on a Chip.

Sean Murray, Will Floyd-Jones, Ying Qi, Daniel J. Sorin, George Dimitri Konidaris

Proceedings of the Robotics: Science and Systems XII, University of Michigan, Ann Arbor, Michigan, USA, June 18, 2016

The microarchitecture of a real-time robot motion planning accelerator.

Sean Murray, William Floyd-Jones, Ying Qi, George Dimitri Konidaris, Daniel J. Sorin

Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Verifiable hierarchical protocols with network invariants on parametric systems.

Opeoluwa Matthews, Jesse D. Bingham, Daniel J. Sorin

Proceedings of the 2016 Formal Methods in Computer-Aided Design, 2016

Methuselah Flash: Rewriting Codes for Extra Long Storage Lifetime.

Georgios Mappouras, Alireza Vahid, A. Robert Calderbank, Daniel J. Sorin

Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2016

2015

PVCoherence: Designing Flat Coherence Protocols for Scalable Verification.

Meng Zhang, Jesse D. Bingham, John Erickson, Daniel J. Sorin

IEEE Micro, 2015

Reduced Precision Checking to Detect Errors in Floating Point Arithmetic.

Yaqi Zhang, Ralph Nathan, Daniel J. Sorin

CoRR, 2015

Argus-G: Comprehensive, Low-Cost Error Detection for GPGPU Cores.

Ralph Nathan, Daniel J. Sorin

IEEE Comput. Archit. Lett., 2015

Writing without Disturb on Phase Change Memories by Integrating Coding and Layout Design.

Ali Eslami, Alfredo Velasco, Alireza Vahid, Georgios Mappouras, A. Robert Calderbank, Daniel J. Sorin

Proceedings of the 2015 International Symposium on Memory Systems, 2015

Multi-program benchmark definition.

Adam N. Jacobvitz, Andrew D. Hilton, Daniel J. Sorin

Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

2014

Recycled Error Bits: Energy-Efficient Architectural Support for Floating Point Accuracy.

Ralph Nathan, Bryan Anthonio, Shih-Lien Lu, Helia Naeimi, Daniel J. Sorin, Xiaobai Sun

Proceedings of the International Conference for High Performance Computing, 2014

Scalably verifiable dynamic power management.

Opeoluwa Matthews, Meng Zhang, Daniel J. Sorin

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

Nostradamus: Low-cost hardware-only error detection for processor cores.

Ralph Nathan, Daniel J. Sorin

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Architecting Dynamic Power Management to be Formally Verifiable.

Daniel J. Sorin, Opeoluwa Matthews, Meng Zhang

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Recycled Error Bits: Energy-Efficient Architectural Support for Higher Precision Floating Point.

Ralph Nathan, Bryan Anthonio, Shih-Lien Lu, Helia Naeimi, Daniel J. Sorin, Xiaobai Sun

CoRR, 2013

Applying Reduced Precision Arithmetic to Detect Errors in Floating Point Multiplication.

Kushal Seetharam, Lance Ong-Siong Co Ting Keh, Ralph Nathan, Daniel J. Sorin

Proceedings of the IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013

Evaluating cache coherent shared virtual memory for heterogeneous multicore chips.

Blake A. Hechtman, Daniel J. Sorin

Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

Exploring memory consistency for massively-threaded throughput-oriented processors.

Blake A. Hechtman, Daniel J. Sorin

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

Coset coding to extend the lifetime of memory.

Adam N. Jacobvitz, A. Robert Calderbank, Daniel J. Sorin

Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2012

Why on-chip cache coherence is here to stay.

Milo M. K. Martin, Mark D. Hill, Daniel J. Sorin

Commun. ACM, 2012

Writing cosets of a convolutional code to increase the Lifetime of Flash memory.

Adam N. Jacobvitz, A. Robert Calderbank, Daniel J. Sorin

Proceedings of the 50th Annual Allerton Conference on Communication, 2012

2011

A Primer on Memory Consistency and Cache Coherence

Daniel J. Sorin, Mark D. Hill, David A. Wood

Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01733-9, 2011

Address Translation Aware Memory Consistency.

Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin

IEEE Micro, 2011

An FPGA-based experimental evaluation of microprocessor core error detection with Argus-2.

Patrick J. Eibl, Albert Meixner, Daniel J. Sorin

Proceedings of the SIGMETRICS 2011, 2011

Architectures for online error detection and recovery in multicore processors.

Dimitris Gizopoulos, Mihalis Psarakis, Sarita V. Adve, Pradeep Ramachandran, Siva Kumar Sastry Hari, Daniel J. Sorin, Albert Meixner, Arijit Biswas, Xavier Vera

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Fractal Consistency: Architecting the Memory System to Facilitate Verification.

Meng Zhang, Alvin R. Lebeck, Daniel J. Sorin

IEEE Comput. Archit. Lett., 2010

Fractal Coherence: Scalably Verifiable Cache Coherence.

Meng Zhang, Alvin R. Lebeck, Daniel J. Sorin

Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

UNified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all.

Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin, Anne Bracy

Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

Specifying and dynamically verifying address translation-aware memory consistency.

Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin

Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010

2009

Fault Tolerant Computer Architecture

Daniel J. Sorin

Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01723-0, 2009

Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures.

Albert Meixner, Daniel J. Sorin

IEEE Trans. Dependable Secur. Comput., 2009

Multicore power management: Ensuring robustness via early-stage formal verification.

Anita Lungu, Pradip Bose, Daniel J. Sorin, Steven German, Geert Janssen

Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), 2009

Dynamic power gating with quality guarantees.

Anita Lungu, Pradip Bose, Alper Buyuktosunoglu, Daniel J. Sorin

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms.

Meng Zhang, Anita Lungu, Daniel J. Sorin

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

Reduced Precision Checking for a Floating Point Adder.

Patrick J. Eibl, Andrew D. Cook, Daniel J. Sorin

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008

Argus: Low-Cost, Comprehensive Error Detection in Simple Cores.

Albert Meixner, Michael E. Bauer, Daniel J. Sorin

IEEE Micro, 2008

The Impact of Dynamically Heterogeneous Multicore Processors on Thread Scheduling.

Fred A. Bower, Daniel J. Sorin, Landon P. Cox

IEEE Micro, 2008

Detouring: Translating software to circumvent hard faults in simple cores.

Albert Meixner, Daniel J. Sorin

Proceedings of the 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2008

Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching.

Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, Daniel J. Sorin

Proceedings of the 5th Conference on Computing Frontiers, 2008

Core cannibalization architecture: improving lifetime chip performance for multicore processors in the presence of hard faults.

Bogdan F. Romanescu, Daniel J. Sorin

Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008

2007

Online diagnosis of hard faults in microprocessors.

Fred A. Bower, Daniel J. Sorin, Sule Ozev

ACM Trans. Archit. Code Optim., 2007

VariaSim: simulating circuits and systems in the presence of process variability.

Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, Daniel J. Sorin

SIGARCH Comput. Archit. News, 2007

Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor.

Sule Ozev, Daniel J. Sorin, Mahmut Yilmaz

Proceedings of the 25th International Conference on Computer Design, 2007

Error Detection via Online Checking of Cache Coherence with Token Coherence Signatures.

Albert Meixner, Daniel J. Sorin

Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007

Lazy Error Detection for Microprocessor Functional Units.

Mahmut Yilmaz, Albert Meixner, Sule Ozev, Daniel J. Sorin

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Unified microprocessor core storage.

Albert Meixner, Daniel J. Sorin

Proceedings of the 4th Conference on Computing Frontiers, 2007

Reducing the Impact of Process Variability with Prefetching and Criticality-Based Resource Allocation.

Bogdan F. Romanescu, Michael E. Bauer, Daniel J. Sorin, Sule Ozev

Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

Error Detection Using Dynamic Dataflow Verification.

Albert Meixner, Daniel J. Sorin

Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

Verification-Aware Microprocessor Design.

Anita Lungu, Daniel J. Sorin

Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006

Spin Detection Hardware for Improved Management of Multithreaded Systems.

Tong Li, Alvin R. Lebeck, Daniel J. Sorin

IEEE Trans. Parallel Distributed Syst., 2006

NANA: A nano-scale active network architecture.

Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck, Daniel J. Sorin

ACM J. Emerg. Technol. Comput. Syst., 2006

Applying architectural vulnerability Analysis to hard faults in the microprocessor.

Fred A. Bower, Derek Hower, Mahmut Yilmaz, Daniel J. Sorin, Sule Ozev

Proceedings of the Joint International Conference on Measurement and Modeling of Computer Systems, 2006

Self-Checking and Self-Diagnosing 32-bit Microprocessor Multiplier.

Mahmut Yilmaz, Derek Hower, Sule Ozev, Daniel J. Sorin

Proceedings of the 2006 IEEE International Test Conference, 2006

Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache.

Nathan Sadler, Daniel J. Sorin

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

2005

Autonomic Microprocessor Execution via Self-Repairing Arrays.

Fred A. Bower, Sule Ozev, Daniel J. Sorin

IEEE Trans. Dependable Secur. Comput., 2005

Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset.

Milo M. K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R. Alameldeen, Kevin E. Moore, Mark D. Hill, David A. Wood

SIGARCH Comput. Archit. News, 2005

Self-Assembled Architectures and the Temporal Aspects of Computing.

Chris Dwyer, Alvin R. Lebeck, Daniel J. Sorin

Computer, 2005

Pulse: A Dynamic Deadlock Detection Mechanism Using Speculative Execution.

Tong Li, Carla Schlatter Ellis, Alvin R. Lebeck, Daniel J. Sorin

Proceedings of the 2005 USENIX Annual Technical Conference, 2005

A Mechanism for Online Diagnosis of Hard Faults in Microprocessors.

Fred A. Bower, Daniel J. Sorin, Sule Ozev

Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 2005

Dynamic Verification of Sequential Consistency.

Albert Meixner, Daniel J. Sorin

Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown.

Jonathan R. Carter, Sule Ozev, Daniel J. Sorin

Proceedings of the 2005 Design, 2005

2004

Communication breakdown: analyzing CPU usage in commercial Web workloads.

Jaidev P. Patwardhan, Alvin R. Lebeck, Daniel J. Sorin

Proceedings of the 2004 IEEE International Symposium on Performance Analysis of Systems and Software, 2004

Using Speculation to Simplify Multiprocessor Design.

Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, David A. Wood

Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Tolerating Hard Faults in Microprocessor Array Structures.

Fred A. Bower, Paul G. Shealy, Sule Ozev, Daniel J. Sorin

Proceedings of the 2004 International Conference on Dependable Systems and Networks (DSN 2004), 28 June, 2004

2003

Analytic Evaluation of Shared-Memory Architectures.

Daniel J. Sorin, Jonathan Lemon, Derek L. Eager, Mary K. Vernon

IEEE Trans. Parallel Distributed Syst., 2003

Simulating a $2M Commercial Server on a $2K PC.

Alaa R. Alameldeen, Milo M. K. Martin, Carl J. Mauer, Kevin E. Moore, Min Xu, Mark D. Hill, David A. Wood, Daniel J. Sorin

Computer, 2003

Quantifying instruction criticality for shared memory multiprocessors.

Tong Li, Alvin R. Lebeck, Daniel J. Sorin

Proceedings of the SPAA 2003: Proceedings of the Fifteenth Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2003

Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors.

Milo M. K. Martin, Pacia J. Harper, Daniel J. Sorin, Mark D. Hill, David A. Wood

Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

Dynamic Verification of End-to-End Multiprocessor Invariants.

Daniel J. Sorin, Mark D. Hill, David A. Wood

Proceedings of the 2003 International Conference on Dependable Systems and Networks (DSN 2003), 2003

2002

Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol.

Daniel J. Sorin, Manoj Plakal, Anne Condon, Mark D. Hill, Milo M. K. Martin, David A. Wood

IEEE Trans. Parallel Distributed Syst., 2002

SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery.

Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, David A. Wood

Proceedings of the 29th International Symposium on Computer Architecture (ISCA 2002), 2002

Bandwidth Adaptive Snooping.

Milo M. K. Martin, Daniel J. Sorin, Mark D. Hill, David A. Wood

Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

2001

Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing.

Milo M. K. Martin, Daniel J. Sorin, Harold W. Cain, Mark D. Hill, Mikko H. Lipasti

Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

2000

AMVA techniques for high service time variability.

Derek L. Eager, Daniel J. Sorin, Mary K. Vernon

Proceedings of the 2000 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, 2000

Timestamp snooping: an approach for extending SMPs.

Milo M. K. Martin, Daniel J. Sorin, Anastassia Ailamaki, Alaa R. Alameldeen, Ross M. Dickson, Carl J. Mauer, Kevin E. Moore, Manoj Plakal, Mark D. Hill, David A. Wood

Proceedings of the ASPLOS-IX Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, 2000

1999

A System-Level Specification Framework for I/O Architectures.

Mark D. Hill, Anne Condon, Manoj Plakal, Daniel J. Sorin

Proceedings of the Eleventh Annual ACM Symposium on Parallel Algorithms and Architectures, 1999

Multicast Snooping: A New Coherence Method Using a Multicast Address Network.

E. Ender Bilir, Ross M. Dickson, Ying Hu, Manoj Plakal, Daniel J. Sorin, Mark D. Hill, David A. Wood

Proceedings of the 26th Annual International Symposium on Computer Architecture, 1999

Using Lamport Clocks to Reason about Relaxed Memory Models.

Anne Condon, Mark D. Hill, Manoj Plakal, Daniel J. Sorin

Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999

1998

Lamport Clocks: Verifying a Directory Cache-Coherence Protocol.

Manoj Plakal, Daniel J. Sorin, Anne Condon, Mark D. Hill

Proceedings of the Tenth Annual ACM Symposium on Parallel Algorithms and Architectures, 1998

Analytic Evaluation of Shared-memory Systems with ILP Processors.

Daniel J. Sorin, Vijay S. Pai, Sarita V. Adve, Mary K. Vernon, David A. Wood

Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998