Daniel J. Friedman

According to our database1, Daniel J. Friedman authored at least 70 papers between 1991 and 2024.

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Bibliography

2024
Characterization of 14nm CMOS Technology At Cryogenic Temperatures Using Dense Addressable Arrays.
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

2023
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links.
IEEE J. Solid State Circuits, 2023

Cryogenic CMOS: design considerations for future quantum computing systems.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023


2022
A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit State Controller in 14-nm FinFET Technology.
IEEE J. Solid State Circuits, 2022





2021
24.1 A 6.2 GHz Single Ended Current Sense Amplifier (CSA) Based Compileable 8T SRAM in 7nm FinFET Technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage.
IEEE J. Solid State Circuits, 2020

2018
SC: Hardware approaches to machine learning and inference.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Scaling Millimeter-Wave Phased Arrays: Challenges and Solutions.
Proceedings of the 2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2018

2017
A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications.
IEEE J. Solid State Circuits, 2017

7.2 A 28GHz 32-element phased-array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communication.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Ultra-low-power analog design.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration.
IEEE J. Solid State Circuits, 2016

10.8 A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2015

10.9 A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A 28 GHz Hybrid PLL in 32 nm SOI CMOS.
IEEE J. Solid State Circuits, 2014

Adaptive Circuit Design Methodology and Test Applied to Millimeter-Wave Circuits.
IEEE Des. Test, 2014


A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing".
IEEE J. Solid State Circuits, June, 2013

A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing.
IEEE J. Solid State Circuits, 2013

An Integral Path Self-Calibration Scheme for a Dual-Loop PLL.
IEEE J. Solid State Circuits, 2013

A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A linearized voltage-controlled oscillator for dual-path phase-locked loops.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

A 60GHz, linear, direct down-conversion mixer with mm-Wave tunability in 32nm CMOS SOI.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects.
IEEE J. Solid State Circuits, 2012

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2012

Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage.
IEEE J. Solid State Circuits, 2012

A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS.
IEEE J. Solid State Circuits, 2012

An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012

A compact low-power 3D I/O in 45nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012


A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012


2011
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
The population health record: concepts, definition, design, and implementation.
J. Am. Medical Informatics Assoc., 2010

2009
A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS.
IEEE J. Solid State Circuits, 2009

A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2009

Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 5.4mW 0.0035mm<sup>2</sup> 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI.
IEEE J. Solid State Circuits, 2008

A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 2.6mW 370MHz-to-2.5GHz Open-Loop Quadrature Clock Generator.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
An Ultra-Compact Differentially Tuned 6-GHz CMOS LC-VCO With Dynamic Common-Mode Feedback.
IEEE J. Solid State Circuits, 2007

A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE.
IEEE J. Solid State Circuits, 2007

A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS AD PLL in 65nm SOI.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 7Gb/s 9.3mW 2-Tap Current-Integrating DFE Receiver.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLs.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology.
IEEE J. Solid State Circuits, 2006

Phase and amplitude pre-emphasis techniques for low-power serial links.
IEEE J. Solid State Circuits, 2006


2004
A semi-digital delay-locked loop using an analog-based finite state machine.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

2003
A 0.18-μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems.
IEEE J. Solid State Circuits, 2003

SiGe BiCMOS integrated circuits for high-speed serial communication links.
IBM J. Res. Dev., 2003

A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

45-Gb/s SiGe BiCMOS PRBS generator and PRBS checker [pseudorandom bit sequence].
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

1991
VLSI sensori-motor systems.
Proceedings of the 1991 IEEE International Conference on Robotics and Automation, 1991


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