Daniel Hackenberg

Orcid: 0000-0002-8491-770X

According to our database1, Daniel Hackenberg authored at least 43 papers between 2006 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Energy Efficiency Features of the Intel Alder Lake Architecture.
Proceedings of the 15th ACM/SPEC International Conference on Performance Engineering, 2024

Calculating User-Centric Carbon Footprints for HPC.
Proceedings of the IEEE International Conference on Cluster Computing, 2024

16 Years of SPEC Power: An Analysis of x86 Energy Efficiency Trends.
Proceedings of the IEEE International Conference on Cluster Computing, 2024

2022
Memory Performance of AMD EPYC Rome and Intel Cascade Lake SP Server Processors.
Proceedings of the ICPE '22: ACM/SPEC International Conference on Performance Engineering, Bejing, China, April 9, 2022

2021
FIRESTARTER 2: Dynamic Code Generation for Processor Stress Tests.
Proceedings of the IEEE International Conference on Cluster Computing, 2021

Energy Efficiency Aspects of the AMD Zen 2 Architecture.
Proceedings of the IEEE International Conference on Cluster Computing, 2021

2019
Power measurement techniques for energy-efficient computing: reconciling scalability, resolution, and accuracy.
SICS Softw.-Intensive Cyber Phys. Syst., 2019

MetricQ: A Scalable Infrastructure for Processing High-Resolution Time Series Data.
Proceedings of the 3rd IEEE/ACM Industry/University Joint International Workshop on Data-center Automation, 2019

Energy Efficiency Features of the Intel Skylake-SP Processor and Their Impact on Performance.
Proceedings of the 17th International Conference on High Performance Computing & Simulation, 2019

2017
The READEX formalism for automatic tuning for energy efficiency.
Computing, 2017

Detecting Memory-Boundedness with Hardware Performance Counters.
Proceedings of the 8th ACM/SPEC on International Conference on Performance Engineering, 2017

Towards fine-grained dynamic tuning of HPC applications on modern multi-core architectures.
Proceedings of the International Conference for High Performance Computing, 2017

Powernightmares: The Challenge of Efficiently Using Sleep States on Multi-core Systems.
Proceedings of the Euro-Par 2017: Parallel Processing Workshops, 2017

lo2s - Multi-core System and Application Performance Analysis for Linux.
Proceedings of the 2017 IEEE International Conference on Cluster Computing, 2017

2016
The shift from processor power consumption to performance variations: fundamental implications at scale.
Comput. Sci. Res. Dev., 2016

Software Controlled Clock Modulation for Energy Efficiency Optimization on Intel Processors.
Proceedings of the 4th International Workshop on Energy Efficient Supercomputing, 2016

2015
Node variability in large-scale power measurements: perspectives from the Green500, Top500 and EEHPCWG.
Proceedings of the International Conference for High Performance Computing, 2015

An Energy Efficiency Feature Survey of the Intel Haswell Processor.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

Cache Coherence Protocol and Memory Performance of the Intel Haswell-EP Architecture.
Proceedings of the 44th International Conference on Parallel Processing, 2015

Power measurements for compute nodes: Improving sampling rates, granularity and accuracy.
Proceedings of the Sixth International Green and Sustainable Computing Conference, 2015

Business Strategy, IT Management and Business Value - a tripartite interaction?
Proceedings of the 21st Americas Conference on Information Systems, 2015

2014
HDEEM: high definition energy efficiency monitoring.
Proceedings of the 2nd International Workshop on Energy Efficient Supercomputing, 2014

Main memory and cache performance of intel sandy bridge and AMD bulldozer.
Proceedings of the workshop on Memory Systems Performance and Correctness, 2014

Analysis of Parallel Applications on a High Performance-Low Energy Computer.
Proceedings of the Euro-Par 2014: Parallel Processing Workshops, 2014

2013
Power measurement techniques on standard compute nodes: A quantitative comparison.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

Introducing FIRESTARTER: A processor stress test utility.
Proceedings of the International Green Computing Conference, 2013

2012
Collecting Distributed Performance Data with Dataheap: Generating and Exploiting a Holistic System View.
Proceedings of the International Conference on Computational Science, 2012

Flexible workload generation for HPC cluster efficiency benchmarking.
Comput. Sci. Res. Dev., 2012

Performance analysis of multi-level parallelism: inter-node, intra-node and hardware accelerators.
Concurr. Comput. Pract. Exp., 2012

Memory Performance at Reduced CPU Clock Speeds: An Analysis of Current x86_64 Processors.
Proceedings of the 2012 Workshop on Power-Aware Computing Systems, HotPower'12, 2012

SPEC OMP2012 - An Application Benchmark Suite for Parallel Systems Using OpenMP.
Proceedings of the OpenMP in a Heterogeneous World - 8th International Workshop on OpenMP, 2012

2011
On-line analysis of hardware performance events for workload characterization and processor frequency scaling decisions.
Proceedings of the ICPE'11, 2011

Simultaneous multithreading on x86_64 systems: an energy efficiency evaluation.
Proceedings of the 4th Workshop on Power-Aware Computing and Systems, 2011

Memory Performance and SPEC OpenMP Scalability on Quad-Socket x86_64 Systems.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2011

2010
Quantifying power consumption variations of HPC systems using SPEC MPI benchmarks.
Comput. Sci. Res. Dev., 2010

Characterizing the energy consumption of data transfers and arithmetic operations on x86-64 processors.
Proceedings of the International Green Computing Conference 2010, 2010

The VampirTrace Plugin Counter Interface: Introduction and Examples.
Proceedings of the Euro-Par 2010 Parallel Processing Workshops, 2010

High Resolution Program Flow Visualization of Hardware Accelerated Hybrid Multi-core Applications.
Proceedings of the 10th IEEE/ACM International Conference on Cluster, 2010

2009
Comprehensive Performance Tracking with Vampir 7.
Proceedings of the Tools for High Performance Computing 2009, 2009

Comparing cache architectures and coherency protocols on x86-64 multicore SMP systems.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Memory Performance and Cache Coherency Effects on an Intel Nehalem Multiprocessor System.
Proceedings of the PACT 2009, 2009

2008
Event Tracing and Visualization for Cell Broadband Engine Systems.
Proceedings of the Euro-Par 2008, 2008

2006
Optimizing OpenMP Parallelized DGEMM Calls on SGI Altix 3700.
Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006


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