Daniel Gomez-Prado

According to our database, Daniel Gomez-Prado authored at least 8 papers between 2004 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2013

FPGA latency optimization using system-level transformations and DFG restructuring.

Daniel Gomez-Prado, Maciej J. Ciesielski, Russell Tessier

Proceedings of the Design, Automation and Test in Europe, 2013

2010

Retiming arithmetic datapaths using Timed Taylor Expansion Diagrams.

Daniel Gomez-Prado, Dusung Kim, Maciej J. Ciesielski, Emmanuel Boutillon

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

2009

Optimization of Data-Flow Computations Using Canonical TED Representation.

Maciej J. Ciesielski, Daniel Gomez-Prado, Qian Ren, Jérémie Guillot, Emmanuel Boutillon

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

High-Level Dataflow Transformations Using Taylor Expansion Diagrams.

Maciej J. Ciesielski, Jérémie Guillot, Daniel Gomez-Prado, Emmanuel Boutillon

IEEE Des. Test Comput., 2009

Optimizing data flow graphs to minimize hardware implementation.

Daniel Gomez-Prado, Qian Ren, Maciej J. Ciesielski, Jérémie Guillot, Emmanuel Boutillon

Proceedings of the Design, Automation and Test in Europe, 2009

2007

Data-flow transformations using Taylor expansion diagrams.

Maciej J. Ciesielski, Serkan Askar, Daniel Gomez-Prado, Jérémie Guillot, Emmanuel Boutillon

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Efficient factorization of DSP transforms using taylor expansion diagrams.

Jérémie Guillot, Emmanuel Boutillon, Qian Ren, Maciej J. Ciesielski, Daniel Gomez-Prado, Serkan Askar

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2004

Variable ordering for taylor expansion diagrams.

Daniel Gomez-Prado, Qian Ren, Serkan Askar, Maciej J. Ciesielski, Emmanuel Boutillon

Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004