Daniel Geist

According to our database1, Daniel Geist authored at least 25 papers between 1989 and 2008.

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Bibliography

2008
A method for hunting bugs that occur due to system conflicts.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

2006
Formal Verification Analysis of Load-Voltage Power Control.
Intell. Autom. Soft Comput., 2006

2005
Supporting SAT based BMC on Finite Path Models.
Proceedings of the Third International Workshop on Bounded Model Checking, 2005

Computing the minimum DNF representation of Boolean functions defined by intervals.
Discret. Appl. Math., 2005

Combining System Level Modeling with Assertion Based Verification.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

2003
Model Checking at IBM.
Formal Methods Syst. Des., 2003

The PSL/Sugar Specification Language A Language for all Seasons.
Proceedings of the Correct Hardware Design and Verification Methods, 2003

Semi-formal test generation and resolving a temporal abstraction problem in practice: industrial application.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
A Scalable Parallel Algorithm for Reachability Analysis of Very Large Circuits.
Formal Methods Syst. Des., 2002

Symbolic Localization Reduction with Reconstruction Layering and Backtracking.
Proceedings of the Computer Aided Verification, 14th International Conference, 2002

2001
On the Effective Deployment of Functional Formal Verification.
Formal Methods Syst. Des., 2001

Semi-Formal Test Generation for a Block of Industrial DSP.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Semi-Formal Test Generation with Genevieve.
Proceedings of the 38th Design Automation Conference, 2001

2000
Achieving Scalability in Parallel Reachability Analysis of Very Large Circuits.
Proceedings of the Computer Aided Verification, 12th International Conference, 2000

1999
A Methodology for the Verification of a "System on Chip".
Proceedings of the 36th Conference on Design Automation, 1999

A Study in Coverage-Driven Test Generation.
Proceedings of the 36th Conference on Design Automation, 1999

"Have I written enough Properties?" - A Method of Comparison between Specification and Implementation.
Proceedings of the Correct Hardware Design and Verification Methods, 1999

1997
RuleBase: Model Checking at IBM.
Proceedings of the Computer Aided Verification, 9th International Conference, 1997

1996
Coverage-Directed Test Generation Using Symbolic Techniques.
Proceedings of the Formal Methods in Computer-Aided Design, First International Conference, 1996

1995
AVPGEN-A test generator for architecture verification.
IEEE Trans. Very Large Scale Integr. Syst., 1995

1994
Efficient Model Checking by Automated Ordering of Transition Relation Partitions.
Proceedings of the Computer Aided Verification, 6th International Conference, 1994

Methodology and System for Practical Formal Verification of Reactive Hardware.
Proceedings of the Computer Aided Verification, 6th International Conference, 1994

1992
Adjacency of the 0-1 knapsack problem.
Comput. Oper. Res., 1992

1989
PC-based 3-D reconstruction of medical images.
Comput. Graph., 1989

Time-variant decision support systems.
Proceedings of the IEEE International Conference on Systems, 1989


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