Daniel E. Holcomb

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024

Memory Scraping Attack on Xilinx FPGAs: Private Data Extraction from Terminated Processes.

[BibT_eX]

[DOI]

Bharadwaj Madabhushi

Sandip Kundu

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

Voltage Sensor Implementations for Remote Power Attacks on FPGAs.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., March, 2023

Jitter-based Adaptive True Random Number Generation Circuits for FPGAs in the Cloud.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., March, 2023

Stealing Maggie's Secrets - On the Challenges of IP Theft Through FPGA Reverse Engineering.

[BibT_eX]

[DOI]

CoRR, 2023

A Secure Design Methodology to Prevent Targeted Trojan Insertion during Fabrication.

[BibT_eX]

[DOI]

Arjun Suresh

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

Fault Recovery from Multi-Tenant FPGA Voltage Attacks.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

A Practical Remote Power Attack on Machine Learning Accelerators in Cloud FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Accelerating BGP Configuration Verification Through Reducing Cycles in SMT Constraints.

[BibT_eX]

[DOI]

IEEE/ACM Trans. Netw., 2022

Know Time to Die - Integrity Checking for Zero Trust Chiplet-based Systems Using Between-Die Delay PUFs.

[BibT_eX]

[DOI]

Aleksa Deric

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

Precise Fault Injection to Enable DFIA for Attacking AES in Remote FPGAs.

[BibT_eX]

[DOI]

Xiang Li

Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

2021

The ASHES 2019 special issue at JCEN.

[BibT_eX]

[DOI]

J. Cryptogr. Eng., 2021

Power Side-Channel Attacks on BNN Accelerators in Remote FPGAs.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

Guest Editors' Introduction: Competing to Secure SoCs.

[BibT_eX]

[DOI]

Siddharth Garg

Jeyavijayan (JV) Rajendran

Ahmad-Reza Sadeghi

IEEE Des. Test, 2021

Characterization of IOBUF-based Ring Oscillators.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2021

Remote Power Attacks on the Versatile Tensor Accelerator in Multi-Tenant FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

Remote Power Side-Channel Attacks on BNN Accelerators in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Power Distribution Attacks in Multitenant FPGAs.

[BibT_eX]

[DOI]

George Provelengios

IEEE Trans. Very Large Scale Integr. Syst., 2020

Efficient Register Renaming Architectures for 8-bit AES Datapath at 0.55 pJ/bit in 16-nm FinFET.

[BibT_eX]

[DOI]

Samuel Allen

IEEE Trans. Very Large Scale Integr. Syst., 2020

Techniques to Reduce Switching and Leakage Energy in Unrolled Block Ciphers.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2020

Remote Power Side-Channel Attacks on CNN Accelerators in FPGAs.

[BibT_eX]

[DOI]

CoRR, 2020

COUNTERFOIL: Verifying Provenance of Integrated Circuits using Intrinsic Package Fingerprints and Inexpensive Cameras.

[BibT_eX]

[DOI]

Xiang Li

Proceedings of the 29th USENIX Security Symposium, 2020

Understanding and Comparing the Capabilities of On-Chip Voltage Sensors against Remote Power Attacks on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Jitter-based Adaptive True Random Number Generation for FPGAs in the Cloud.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2020

Power Wasting Circuits for Cloud FPGA Attacks.

[BibT_eX]

[DOI]

George Provelengios

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2019

Efficient PUF-Based Key Generation in FPGAs Using Per-Device Configuration.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Loop Unrolling for Energy Efficiency in Low-Cost Field-Programmable Gate Arrays.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2019

Temperature-Based Hardware Trojan For Ring-Oscillator-Based TRNGs.

[BibT_eX]

[DOI]

Samaneh Ghandali

Christof Paar

CoRR, 2019

Enabling Microarchitectural Randomization in Serialized AES Implementations to Mitigate Side Channel Susceptibility.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Characterizing Power Distribution Attacks in Multi-User FPGA Environments.

[BibT_eX]

[DOI]

George Provelengios

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Characterization of Long Wire Data Leakage in Deep Submicron FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

ASHES 2019: 3rd Workshop on Attacks and Solutions in Hardware Security.

[BibT_eX]

[DOI]

Proceedings of the 2019 ACM SIGSAC Conference on Computer and Communications Security, 2019

2018

Bimodal Oscillation as a Mechanism for Autonomous Majority Voting in PUFs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Survey on Applications of Formal Methods in Reverse Engineering and Intellectual Property Protection.

[BibT_eX]

[DOI]

J. Hardw. Syst. Secur., 2018

Algorithmic Obfuscation over GF(2<sup>m</sup>).

[BibT_eX]

[DOI]

Cunxi Yu

CoRR, 2018

SAT-based reverse engineering of gate-level schematics using fault injection and probing.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

FPGA Side Channel Attacks without Physical Access.

[BibT_eX]

[DOI]

Chethan Ramesh

Shivukumar B. Patil

Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

ASHES 2018- Workshop on Attacks and Solutions in Hardware Security.

[BibT_eX]

[DOI]

Proceedings of the 2018 ACM SIGSAC Conference on Computer and Communications Security, 2018

2017

Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques.

[BibT_eX]

[DOI]

Arunkumar Vijayakumar

IEEE Trans. Inf. Forensics Secur., 2017

Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

An improved clocking methodology for energy efficient low area AES architectures using register renaming.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Privacy leakages in approximate adders.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Threshold-based obfuscated keys with quantifiable security against invasive readout.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Improving reliability of weak PUFs via circuit techniques to enhance mismatch.

[BibT_eX]

[DOI]

Vinay C. Patil

Arunkumar Vijayakumar

Sandip Kundu

Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Energy Efficient Loop Unrolling for Low-Cost FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

Reverse engineering of irreducible polynomials in GF(2<sup>m</sup>) arithmetic.

[BibT_eX]

[DOI]

Cunxi Yu

Maciej J. Ciesielski

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Design automation for obfuscated circuits with multiple viable functions.

[BibT_eX]

[DOI]

Christof Paar

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Persistent Clocks for Batteryless Sensing Devices.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2016

A Design Methodology for Stealthy Parametric Trojans and Its Application to Bug Attacks.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2016

Energy Optimization of Unrolled Block Ciphers using Combinational Checkpointing.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2016

Reverse Engineering of Irreducible Polynomials in GF(2^m) Arithmetic.

[BibT_eX]

[DOI]

Cunxi Yu

Maciej J. Ciesielski

CoRR, 2016

Using Statistical Models to Improve the Reliability of Delay-Based PUFs.

[BibT_eX]

[DOI]

Xiaolin Xu

Wayne P. Burleson

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

LLPA: Logic State Based Leakage Power Analysis.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

A Clockless Sequential PUF with Autonomous Majority Voting.

[BibT_eX]

[DOI]

Xiaolin Xu

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Improving the efficiency of PUF-based key generation in FPGAs using variation-aware placement.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Reliable PUF design using failure patterns from time-controlled power gating.

[BibT_eX]

[DOI]

Xiaolin Xu

Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

Oracle-guided incremental SAT solving to reverse engineer camouflaged logic circuits.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Reliable Physical Unclonable Functions Using Data Retention Voltage of SRAM Cells.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Security Evaluation and Enhancement of Bistable Ring PUFs.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2015

Probable cause: the deanonymizing effects of approximate DRAM.

[BibT_eX]

[DOI]

Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

2014

Compositional Performance Verification of Network-on-Chip Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Bitline PUF: Building Native Challenge-Response PUF Capability into Any SRAM.

[BibT_eX]

[DOI]

Kevin Fu

IACR Cryptol. ePrint Arch., 2014

PUFs at a glance.

[BibT_eX]

[DOI]

Ulrich Rührmair

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Formal Verification and Synthesis for Quality-of-Service in On-Chip Networks

[BibT_eX]

[DOI]

PhD thesis, 2013

2012

TARDIS: Time and Remanence Decay in SRAM to Implement Secure Protocols on Embedded Devices without Clocks.

[BibT_eX]

[DOI]

Proceedings of the 21th USENIX Security Symposium, Bellevue, WA, USA, August 8-10, 2012, 2012

DRV-Fingerprinting: Using Data Retention Voltage of SRAM Cells for Chip Identification.

[BibT_eX]

[DOI]

Proceedings of the Radio Frequency Identification. Security and Privacy Issues, 2012

Compositional performance verification of NoC designs.

[BibT_eX]

[DOI]

Proceedings of the Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2012

2011

Counterexample-guided SMT-driven optimal buffer sizing.

[BibT_eX]

[DOI]

Bryan A. Brady

Proceedings of the Design, Automation and Test in Europe, 2011

Abstraction-based performance verification of NoCs.

[BibT_eX]

[DOI]

Bryan A. Brady

Proceedings of the 48th Design Automation Conference, 2011

2010

Low-power sub-threshold design of secure physical unclonable functions.

[BibT_eX]

[DOI]

Lang Lin

Dilip Kumar Krishnappa

Prasad Shabadi

Wayne P. Burleson

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

2009

Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers.

[BibT_eX]

[DOI]

Wayne P. Burleson

Kevin Fu

IEEE Trans. Computers, 2009

Design as you see FIT: System-level soft error analysis of sequential circuits.

[BibT_eX]

[DOI]

Wenchao Li